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Merge pull request #1406 from whitequark/connect_rpc
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
31
32 YOSYS_NAMESPACE_BEGIN
33
34 // see maccmap.cc
35 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
36
37 YOSYS_NAMESPACE_END
38
39 USING_YOSYS_NAMESPACE
40 PRIVATE_NAMESPACE_BEGIN
41
42 void apply_prefix(IdString prefix, IdString &id)
43 {
44 if (id[0] == '\\')
45 id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
46 else
47 id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
48 }
49
50 void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
51 {
52 vector<SigChunk> chunks = sig;
53 for (auto &chunk : chunks)
54 if (chunk.wire != NULL) {
55 IdString wire_name = chunk.wire->name;
56 apply_prefix(prefix, wire_name);
57 log_assert(module->wires_.count(wire_name) > 0);
58 chunk.wire = module->wires_[wire_name];
59 }
60 sig = chunks;
61 }
62
63 struct TechmapWorker
64 {
65 std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
66 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
67 std::map<RTLIL::Module*, bool> techmap_do_cache;
68 std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
69 dict<Module*, SigMap> sigmaps;
70
71 pool<IdString> flatten_do_list;
72 pool<IdString> flatten_done_list;
73 pool<Cell*> flatten_keep_list;
74
75 pool<string> log_msg_cache;
76
77 struct TechmapWireData {
78 RTLIL::Wire *wire;
79 RTLIL::SigSpec value;
80 };
81
82 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
83
84 bool extern_mode;
85 bool assert_mode;
86 bool flatten_mode;
87 bool recursive_mode;
88 bool autoproc_mode;
89 bool ignore_wb;
90
91 TechmapWorker()
92 {
93 extern_mode = false;
94 assert_mode = false;
95 flatten_mode = false;
96 recursive_mode = false;
97 autoproc_mode = false;
98 ignore_wb = false;
99 }
100
101 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
102 {
103 std::string constmap_info;
104 std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
105
106 for (auto conn : cell->connections())
107 for (int i = 0; i < GetSize(conn.second); i++) {
108 RTLIL::SigBit bit = sigmap(conn.second[i]);
109 if (bit.wire == nullptr) {
110 if (verbose)
111 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
112 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
113 } else if (connbits_map.count(bit)) {
114 if (verbose)
115 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
116 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
117 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
118 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
119 } else {
120 connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
121 constmap_info += stringf("|%s %d", log_id(conn.first), i);
122 }
123 }
124
125 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
126 }
127
128 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
129 {
130 TechmapWires result;
131
132 if (module == NULL)
133 return result;
134
135 for (auto &it : module->wires_) {
136 const char *p = it.first.c_str();
137 if (*p == '$')
138 continue;
139
140 const char *q = strrchr(p+1, '.');
141 p = q ? q+1 : p+1;
142
143 if (!strncmp(p, "_TECHMAP_", 9)) {
144 TechmapWireData record;
145 record.wire = it.second;
146 record.value = it.second;
147 result[p].push_back(record);
148 it.second->attributes[ID::keep] = RTLIL::Const(1);
149 it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
150 }
151 }
152
153 if (!result.empty()) {
154 SigMap sigmap(module);
155 for (auto &it1 : result)
156 for (auto &it2 : it1.second)
157 sigmap.apply(it2.value);
158 }
159
160 return result;
161 }
162
163 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
164 {
165 if (tpl->processes.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it : tpl->processes)
168 log(" %s",RTLIL::id2cstr(it.first));
169 log("\n");
170 if (autoproc_mode) {
171 Pass::call_on_module(tpl->design, tpl, "proc");
172 log_assert(GetSize(tpl->processes) == 0);
173 } else
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
175 }
176
177 std::string orig_cell_name;
178 pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
179
180 if (!flatten_mode) {
181 for (auto &it : tpl->cells_)
182 if (it.first == ID(_TECHMAP_REPLACE_)) {
183 orig_cell_name = cell->name.str();
184 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
185 break;
186 }
187 }
188
189 dict<IdString, IdString> memory_renames;
190
191 for (auto &it : tpl->memories) {
192 IdString m_name = it.first;
193 apply_prefix(cell->name, m_name);
194 RTLIL::Memory *m = new RTLIL::Memory;
195 m->name = m_name;
196 m->width = it.second->width;
197 m->start_offset = it.second->start_offset;
198 m->size = it.second->size;
199 m->attributes = it.second->attributes;
200 if (m->attributes.count(ID(src)))
201 m->add_strpool_attribute(ID(src), extra_src_attrs);
202 module->memories[m->name] = m;
203 memory_renames[it.first] = m->name;
204 design->select(module, m);
205 }
206
207 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
208 dict<Wire*, IdString> temp_renamed_wires;
209 pool<SigBit> autopurge_tpl_bits;
210
211 for (auto &it : tpl->wires_)
212 {
213 if (it.second->port_id > 0)
214 {
215 IdString posportname = stringf("$%d", it.second->port_id);
216 positional_ports[posportname] = it.first;
217
218 if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
219 (!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
220 (!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
221 {
222 if (sigmaps.count(tpl) == 0)
223 sigmaps[tpl].set(tpl);
224
225 for (auto bit : sigmaps.at(tpl)(it.second))
226 if (bit.wire != nullptr)
227 autopurge_tpl_bits.insert(bit);
228 }
229 }
230 IdString w_name = it.second->name;
231 apply_prefix(cell->name, w_name);
232 RTLIL::Wire *w = module->wire(w_name);
233 if (w != nullptr) {
234 if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
235 temp_renamed_wires[w] = w->name;
236 module->rename(w, NEW_ID);
237 w = nullptr;
238 } else {
239 w->attributes.erase(ID(hierconn));
240 if (GetSize(w) < GetSize(it.second)) {
241 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
242 log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
243 w->width = GetSize(it.second);
244 }
245 }
246 }
247 if (w == nullptr) {
248 w = module->addWire(w_name, it.second);
249 w->port_input = false;
250 w->port_output = false;
251 w->port_id = 0;
252 if (!flatten_mode)
253 w->attributes.erase(ID(techmap_autopurge));
254 if (it.second->get_bool_attribute(ID(_techmap_special_)))
255 w->attributes.clear();
256 if (w->attributes.count(ID(src)))
257 w->add_strpool_attribute(ID(src), extra_src_attrs);
258 }
259 design->select(module, w);
260 }
261
262 SigMap tpl_sigmap(tpl);
263 pool<SigBit> tpl_written_bits;
264
265 for (auto &it1 : tpl->cells_)
266 for (auto &it2 : it1.second->connections_)
267 if (it1.second->output(it2.first))
268 for (auto bit : tpl_sigmap(it2.second))
269 tpl_written_bits.insert(bit);
270 for (auto &it1 : tpl->connections_)
271 for (auto bit : tpl_sigmap(it1.first))
272 tpl_written_bits.insert(bit);
273
274 SigMap port_signal_map;
275 SigSig port_signal_assign;
276
277 for (auto &it : cell->connections())
278 {
279 RTLIL::IdString portname = it.first;
280 if (positional_ports.count(portname) > 0)
281 portname = positional_ports.at(portname);
282 if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
283 if (portname.begins_with("$"))
284 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
285 continue;
286 }
287
288 if (GetSize(it.second) == 0)
289 continue;
290
291 RTLIL::Wire *w = tpl->wires_.at(portname);
292 RTLIL::SigSig c, extra_connect;
293
294 if (w->port_output && !w->port_input) {
295 c.first = it.second;
296 c.second = RTLIL::SigSpec(w);
297 apply_prefix(cell->name, c.second, module);
298 extra_connect.first = c.second;
299 extra_connect.second = c.first;
300 } else if (!w->port_output && w->port_input) {
301 c.first = RTLIL::SigSpec(w);
302 c.second = it.second;
303 apply_prefix(cell->name, c.first, module);
304 extra_connect.first = c.first;
305 extra_connect.second = c.second;
306 } else {
307 SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
308 apply_prefix(cell->name, sig_tpl_pf, module);
309 for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
310 if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
311 c.first.append(sig_mod[i]);
312 c.second.append(sig_tpl_pf[i]);
313 } else {
314 c.first.append(sig_tpl_pf[i]);
315 c.second.append(sig_mod[i]);
316 }
317 }
318 extra_connect.first = sig_tpl_pf;
319 extra_connect.second = sig_mod;
320 }
321
322 if (c.second.size() > c.first.size())
323 c.second.remove(c.first.size(), c.second.size() - c.first.size());
324
325 if (c.second.size() < c.first.size())
326 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
327
328 log_assert(c.first.size() == c.second.size());
329
330 if (flatten_mode)
331 {
332 // more conservative approach:
333 // connect internal and external wires
334
335 if (sigmaps.count(module) == 0)
336 sigmaps[module].set(module);
337
338 if (sigmaps.at(module)(c.first).has_const())
339 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
340 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
341
342 module->connect(c);
343 }
344 else
345 {
346 // approach that yields nicer outputs:
347 // replace internal wires that are connected to external wires
348
349 if (w->port_output && !w->port_input) {
350 port_signal_map.add(c.second, c.first);
351 } else
352 if (!w->port_output && w->port_input) {
353 port_signal_map.add(c.first, c.second);
354 } else {
355 module->connect(c);
356 extra_connect = SigSig();
357 }
358
359 for (auto &attr : w->attributes) {
360 if (attr.first == ID(src))
361 continue;
362 auto lhs = GetSize(extra_connect.first);
363 auto rhs = GetSize(extra_connect.second);
364 if (lhs > rhs)
365 extra_connect.first.remove(rhs, lhs-rhs);
366 else if (rhs > lhs)
367 extra_connect.second.remove(lhs, rhs-lhs);
368 module->connect(extra_connect);
369 break;
370 }
371 }
372 }
373
374 for (auto &it : tpl->cells_)
375 {
376 IdString c_name = it.second->name.str();
377 bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
378
379 if (techmap_replace_cell)
380 c_name = orig_cell_name;
381 else
382 apply_prefix(cell->name, c_name);
383
384 RTLIL::Cell *c = module->addCell(c_name, it.second);
385 design->select(module, c);
386
387 if (!flatten_mode && c->type.begins_with("\\$"))
388 c->type = c->type.substr(1);
389
390 vector<IdString> autopurge_ports;
391
392 for (auto &it2 : c->connections_)
393 {
394 bool autopurge = false;
395 if (!autopurge_tpl_bits.empty()) {
396 autopurge = GetSize(it2.second) != 0;
397 for (auto &bit : sigmaps.at(tpl)(it2.second))
398 if (!autopurge_tpl_bits.count(bit)) {
399 autopurge = false;
400 break;
401 }
402 }
403
404 if (autopurge) {
405 autopurge_ports.push_back(it2.first);
406 } else {
407 apply_prefix(cell->name, it2.second, module);
408 port_signal_map.apply(it2.second);
409 }
410 }
411
412 for (auto &it2 : autopurge_ports)
413 c->unsetPort(it2);
414
415 if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
416 IdString memid = c->getParam(ID(MEMID)).decode_string();
417 log_assert(memory_renames.count(memid) != 0);
418 c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
419 }
420
421 if (c->type == ID($mem)) {
422 IdString memid = c->getParam(ID(MEMID)).decode_string();
423 apply_prefix(cell->name, memid);
424 c->setParam(ID(MEMID), Const(memid.c_str()));
425 }
426
427 if (c->attributes.count(ID(src)))
428 c->add_strpool_attribute(ID(src), extra_src_attrs);
429
430 if (techmap_replace_cell)
431 for (auto attr : cell->attributes)
432 if (!c->attributes.count(attr.first))
433 c->attributes[attr.first] = attr.second;
434 }
435
436 for (auto &it : tpl->connections()) {
437 RTLIL::SigSig c = it;
438 apply_prefix(cell->name.str(), c.first, module);
439 apply_prefix(cell->name.str(), c.second, module);
440 port_signal_map.apply(c.first);
441 port_signal_map.apply(c.second);
442 module->connect(c);
443 }
444
445 module->remove(cell);
446
447 for (auto &it : temp_renamed_wires)
448 {
449 Wire *w = it.first;
450 IdString name = it.second;
451 IdString altname = module->uniquify(name);
452 Wire *other_w = module->wire(name);
453 module->rename(other_w, altname);
454 module->rename(w, name);
455 }
456 }
457
458 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
459 const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
460 {
461 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
462
463 if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
464 return false;
465
466 bool log_continue = false;
467 bool did_something = false;
468 LogMakeDebugHdl mkdebug;
469
470 SigMap sigmap(module);
471
472 dict<SigBit, State> init_bits;
473 pool<SigBit> remove_init_bits;
474
475 for (auto wire : module->wires()) {
476 if (wire->attributes.count("\\init")) {
477 Const value = wire->attributes.at("\\init");
478 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
479 if (value[i] != State::Sx)
480 init_bits[sigmap(SigBit(wire, i))] = value[i];
481 }
482 }
483
484 TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
485 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
486 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
487
488 for (auto cell : module->cells())
489 {
490 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
491 continue;
492
493 std::string cell_type = cell->type.str();
494 if (in_recursion && cell->type.begins_with("\\$"))
495 cell_type = cell_type.substr(1);
496
497 if (celltypeMap.count(cell_type) == 0) {
498 if (assert_mode && cell_type.back() != '_')
499 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
500 continue;
501 }
502
503 if (flatten_mode) {
504 bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
505 for (auto &tpl_name : celltypeMap.at(cell_type))
506 if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
507 keepit = true;
508 if (keepit) {
509 if (!flatten_keep_list[cell]) {
510 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
511 flatten_keep_list.insert(cell);
512 }
513 if (!flatten_done_list[cell->type])
514 flatten_do_list.insert(cell->type);
515 continue;
516 }
517 }
518
519 for (auto &conn : cell->connections())
520 {
521 RTLIL::SigSpec sig = sigmap(conn.second);
522 sig.remove_const();
523
524 if (GetSize(sig) == 0)
525 continue;
526
527 for (auto &tpl_name : celltypeMap.at(cell_type)) {
528 RTLIL::Module *tpl = map->modules_[tpl_name];
529 RTLIL::Wire *port = tpl->wire(conn.first);
530 if (port && port->port_input)
531 cell_to_inbit[cell].insert(sig.begin(), sig.end());
532 if (port && port->port_output)
533 for (auto &bit : sig)
534 outbit_to_cell[bit].insert(cell);
535 }
536 }
537
538 cells.node(cell);
539 }
540
541 for (auto &it_right : cell_to_inbit)
542 for (auto &it_sigbit : it_right.second)
543 for (auto &it_left : outbit_to_cell[it_sigbit])
544 cells.edge(it_left, it_right.first);
545
546 cells.sort();
547
548 for (auto cell : cells.sorted)
549 {
550 log_assert(handled_cells.count(cell) == 0);
551 log_assert(cell == module->cell(cell->name));
552 bool mapped_cell = false;
553
554 std::string cell_type = cell->type.str();
555
556 if (in_recursion && cell->type.begins_with("\\$"))
557 cell_type = cell_type.substr(1);
558
559 for (auto &tpl_name : celltypeMap.at(cell_type))
560 {
561 RTLIL::IdString derived_name = tpl_name;
562 RTLIL::Module *tpl = map->modules_[tpl_name];
563 std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
564
565 if (tpl->get_blackbox_attribute(ignore_wb))
566 continue;
567
568 if (!flatten_mode)
569 {
570 std::string extmapper_name;
571
572 if (tpl->get_bool_attribute(ID(techmap_simplemap)))
573 extmapper_name = "simplemap";
574
575 if (tpl->get_bool_attribute(ID(techmap_maccmap)))
576 extmapper_name = "maccmap";
577
578 if (tpl->attributes.count(ID(techmap_wrap)))
579 extmapper_name = "wrap";
580
581 if (!extmapper_name.empty())
582 {
583 cell->type = cell_type;
584
585 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
586 {
587 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
588
589 for (auto &c : cell->parameters)
590 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
591
592 if (extmapper_name == "wrap")
593 m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
594
595 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
596 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
597
598 if (extmapper_module == nullptr)
599 {
600 extmapper_module = extmapper_design->addModule(m_name);
601 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
602
603 extmapper_cell->set_src_attribute(cell->get_src_attribute());
604
605 int port_counter = 1;
606 for (auto &c : extmapper_cell->connections_) {
607 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
608 if (w->name.in(ID::Y, ID(Q)))
609 w->port_output = true;
610 else
611 w->port_input = true;
612 w->port_id = port_counter++;
613 c.second = w;
614 }
615
616 extmapper_module->fixup_ports();
617 extmapper_module->check();
618
619 if (extmapper_name == "simplemap") {
620 log("Creating %s with simplemap.\n", log_id(extmapper_module));
621 if (simplemap_mappers.count(extmapper_cell->type) == 0)
622 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
623 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
624 extmapper_module->remove(extmapper_cell);
625 }
626
627 if (extmapper_name == "maccmap") {
628 log("Creating %s with maccmap.\n", log_id(extmapper_module));
629 if (extmapper_cell->type != ID($macc))
630 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
631 maccmap(extmapper_module, extmapper_cell);
632 extmapper_module->remove(extmapper_cell);
633 }
634
635 if (extmapper_name == "wrap") {
636 std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
637 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
638 mkdebug.on();
639 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
640 log_continue = true;
641 }
642 }
643
644 cell->type = extmapper_module->name;
645 cell->parameters.clear();
646
647 if (!extern_mode || in_recursion) {
648 tpl = extmapper_module;
649 goto use_wrapper_tpl;
650 }
651
652 auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
653 if (!log_msg_cache.count(msg)) {
654 log_msg_cache.insert(msg);
655 log("%s\n", msg.c_str());
656 }
657 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
658 }
659 else
660 {
661 auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
662 if (!log_msg_cache.count(msg)) {
663 log_msg_cache.insert(msg);
664 log("%s\n", msg.c_str());
665 }
666 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
667
668 if (extmapper_name == "simplemap") {
669 if (simplemap_mappers.count(cell->type) == 0)
670 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
671 simplemap_mappers.at(cell->type)(module, cell);
672 }
673
674 if (extmapper_name == "maccmap") {
675 if (cell->type != ID($macc))
676 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
677 maccmap(module, cell);
678 }
679
680 module->remove(cell);
681 cell = NULL;
682 }
683
684 did_something = true;
685 mapped_cell = true;
686 break;
687 }
688
689 for (auto conn : cell->connections()) {
690 if (conn.first.begins_with("$"))
691 continue;
692 if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
693 continue;
694 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
695 goto next_tpl;
696 parameters[conn.first] = conn.second.as_const();
697 }
698
699 if (0) {
700 next_tpl:
701 continue;
702 }
703
704 if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
705 parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
706
707 for (auto conn : cell->connections()) {
708 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
709 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
710 for (auto &bit : v)
711 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
712 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
713 }
714 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
715 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
716 for (auto &bit : v)
717 if (bit.wire != NULL)
718 bit = RTLIL::SigBit(RTLIL::State::Sx);
719 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
720 }
721 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
722 auto sig = sigmap(conn.second);
723 RTLIL::Const value(State::Sx, sig.size());
724 for (int i = 0; i < sig.size(); i++) {
725 auto it = init_bits.find(sig[i]);
726 if (it != init_bits.end()) {
727 value[i] = it->second;
728 }
729 }
730 parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
731 }
732 }
733
734 int unique_bit_id_counter = 0;
735 std::map<RTLIL::SigBit, int> unique_bit_id;
736 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
737 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
738 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
739 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
740
741 for (auto conn : cell->connections())
742 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
743 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
744 if (unique_bit_id.count(bit) == 0)
745 unique_bit_id[bit] = unique_bit_id_counter++;
746 }
747
748 // Find highest bit set
749 int bits = 0;
750 for (int i = 0; i < 32; i++)
751 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
752 bits = i;
753 // Increment index by one to get number of bits
754 bits++;
755 if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
756 parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
757
758 for (auto conn : cell->connections())
759 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
760 RTLIL::Const value;
761 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
762 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
763 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
764 }
765 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
766 }
767 }
768
769 if (0) {
770 use_wrapper_tpl:;
771 // do not register techmap_wrap modules with techmap_cache
772 } else {
773 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
774 if (techmap_cache.count(key) > 0) {
775 tpl = techmap_cache[key];
776 } else {
777 if (parameters.size() != 0) {
778 mkdebug.on();
779 derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
780 tpl = map->module(derived_name);
781 log_continue = true;
782 }
783 techmap_cache[key] = tpl;
784 }
785 }
786
787 if (flatten_mode) {
788 techmap_do_cache[tpl] = true;
789 } else {
790 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
791 if (constmapped_tpl != nullptr)
792 tpl = constmapped_tpl;
793 }
794
795 if (techmap_do_cache.count(tpl) == 0)
796 {
797 bool keep_running = true;
798 techmap_do_cache[tpl] = true;
799
800 std::set<std::string> techmap_wire_names;
801
802 while (keep_running)
803 {
804 TechmapWires twd = techmap_find_special_wires(tpl);
805 keep_running = false;
806
807 for (auto &it : twd)
808 techmap_wire_names.insert(it.first);
809
810 for (auto &it : twd["_TECHMAP_FAIL_"]) {
811 RTLIL::SigSpec value = it.value;
812 if (value.is_fully_const() && value.as_bool()) {
813 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
814 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
815 techmap_do_cache[tpl] = false;
816 }
817 }
818
819 if (!techmap_do_cache[tpl])
820 break;
821
822 for (auto &it : twd)
823 {
824 if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
825 continue;
826
827 auto &data = it.second.front();
828
829 if (!data.value.is_fully_const())
830 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
831
832 techmap_wire_names.erase(it.first);
833
834 const char *p = data.wire->name.c_str();
835 const char *q = strrchr(p+1, '.');
836 q = q ? q : p+1;
837
838 std::string cmd_string = data.value.as_const().decode_string();
839
840 restart_eval_cmd_string:
841 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
842 {
843 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
844
845 log("Analyzing pattern of constant bits for this cell:\n");
846 RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
847 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
848 log_assert(map->module(new_tpl_name) == nullptr);
849
850 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
851 tpl->cloneInto(new_tpl);
852
853 techmap_do_cache.erase(tpl);
854 techmap_do_cache[new_tpl] = true;
855 tpl = new_tpl;
856
857 std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
858 std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
859 std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
860
861 for (auto wire : tpl->wires().to_vector())
862 {
863 if (!wire->port_input || wire->port_output)
864 continue;
865
866 RTLIL::IdString port_name = wire->name;
867 tpl->rename(wire, NEW_ID);
868
869 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
870 wire->port_input = false;
871 wire->port_id = 0;
872
873 for (int i = 0; i < wire->width; i++) {
874 port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
875 port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
876 }
877 }
878
879 for (auto conn : cell->connections())
880 for (int i = 0; i < GetSize(conn.second); i++)
881 {
882 RTLIL::SigBit bit = sigmap(conn.second[i]);
883 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
884
885 if (bit.wire == nullptr)
886 {
887 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
888 port_connmap.at(oldbit) = bit;
889 }
890 else if (cellbits_to_tplbits.count(bit))
891 {
892 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
893 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
894 }
895 else
896 cellbits_to_tplbits[bit] = tplbit;
897 }
898
899 RTLIL::SigSig port_conn;
900 for (auto &it : port_connmap) {
901 port_conn.first.append_bit(it.first);
902 port_conn.second.append_bit(it.second);
903 }
904 tpl->connect(port_conn);
905
906 tpl->check();
907 goto restart_eval_cmd_string;
908 }
909
910 if (cmd_string.rfind("RECURSION; ", 0) == 0)
911 {
912 cmd_string = cmd_string.substr(strlen("RECURSION; "));
913 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
914 goto restart_eval_cmd_string;
915 }
916
917 Pass::call_on_module(map, tpl, cmd_string);
918
919 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
920 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
921 while (tpl->wires_.count(new_name))
922 new_name += "_";
923 tpl->rename(data.wire->name, new_name);
924
925 keep_running = true;
926 break;
927 }
928 }
929
930 TechmapWires twd = techmap_find_special_wires(tpl);
931 for (auto &it : twd) {
932 if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
933 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
934 if (techmap_do_cache[tpl])
935 for (auto &it2 : it.second)
936 if (!it2.value.is_fully_const())
937 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
938 techmap_wire_names.erase(it.first);
939 }
940
941 for (auto &it : techmap_wire_names)
942 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
943
944 if (recursive_mode) {
945 if (log_continue) {
946 log_header(design, "Continuing TECHMAP pass.\n");
947 log_continue = false;
948 mkdebug.off();
949 }
950 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
951 }
952 }
953
954 if (techmap_do_cache.at(tpl) == false)
955 continue;
956
957 if (log_continue) {
958 log_header(design, "Continuing TECHMAP pass.\n");
959 log_continue = false;
960 mkdebug.off();
961 }
962
963 TechmapWires twd = techmap_find_special_wires(tpl);
964 for (auto &it : twd) {
965 if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_") {
966 for (auto &it2 : it.second) {
967 auto val = it2.value.as_const();
968 auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
969 auto it = cell->connections().find(wirename);
970 if (it != cell->connections().end()) {
971 auto sig = sigmap(it->second);
972 for (int i = 0; i < sig.size(); i++)
973 if (val[i] == State::S1)
974 remove_init_bits.insert(sig[i]);
975 }
976 }
977 }
978 }
979
980 if (extern_mode && !in_recursion)
981 {
982 std::string m_name = stringf("$extern:%s", log_id(tpl));
983
984 if (!design->module(m_name))
985 {
986 RTLIL::Module *m = design->addModule(m_name);
987 tpl->cloneInto(m);
988
989 for (auto cell : m->cells()) {
990 if (cell->type.begins_with("\\$"))
991 cell->type = cell->type.substr(1);
992 }
993
994 module_queue.insert(m);
995 }
996
997 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
998 cell->type = m_name;
999 cell->parameters.clear();
1000 }
1001 else
1002 {
1003 auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
1004 if (!log_msg_cache.count(msg)) {
1005 log_msg_cache.insert(msg);
1006 log("%s\n", msg.c_str());
1007 }
1008 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
1009 techmap_module_worker(design, module, cell, tpl);
1010 cell = NULL;
1011 }
1012 did_something = true;
1013 mapped_cell = true;
1014 break;
1015 }
1016
1017 if (assert_mode && !mapped_cell)
1018 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
1019
1020 handled_cells.insert(cell);
1021 }
1022
1023 if (!remove_init_bits.empty()) {
1024 for (auto wire : module->wires())
1025 if (wire->attributes.count("\\init")) {
1026 Const &value = wire->attributes.at("\\init");
1027 bool do_cleanup = true;
1028 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
1029 SigBit bit = sigmap(SigBit(wire, i));
1030 if (remove_init_bits.count(bit))
1031 value[i] = State::Sx;
1032 else if (value[i] != State::Sx)
1033 do_cleanup = false;
1034 }
1035 if (do_cleanup) {
1036 log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
1037 wire->attributes.erase("\\init");
1038 }
1039 }
1040 }
1041
1042 if (log_continue) {
1043 log_header(design, "Continuing TECHMAP pass.\n");
1044 log_continue = false;
1045 mkdebug.off();
1046 }
1047
1048 return did_something;
1049 }
1050 };
1051
1052 struct TechmapPass : public Pass {
1053 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1054 void help() YS_OVERRIDE
1055 {
1056 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1057 log("\n");
1058 log(" techmap [-map filename] [selection]\n");
1059 log("\n");
1060 log("This pass implements a very simple technology mapper that replaces cells in\n");
1061 log("the design with implementations given in form of a Verilog or ilang source\n");
1062 log("file.\n");
1063 log("\n");
1064 log(" -map filename\n");
1065 log(" the library of cell implementations to be used.\n");
1066 log(" without this parameter a builtin library is used that\n");
1067 log(" transforms the internal RTL cells to the internal gate\n");
1068 log(" library.\n");
1069 log("\n");
1070 log(" -map %%<design-name>\n");
1071 log(" like -map above, but with an in-memory design instead of a file.\n");
1072 log("\n");
1073 log(" -extern\n");
1074 log(" load the cell implementations as separate modules into the design\n");
1075 log(" instead of inlining them.\n");
1076 log("\n");
1077 log(" -max_iter <number>\n");
1078 log(" only run the specified number of iterations on each module.\n");
1079 log(" default: unlimited\n");
1080 log("\n");
1081 log(" -recursive\n");
1082 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1083 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1084 log(" but may differ in performance.\n");
1085 log("\n");
1086 log(" -autoproc\n");
1087 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1088 log("\n");
1089 log(" -wb\n");
1090 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1091 log("\n");
1092 log(" -assert\n");
1093 log(" this option will cause techmap to exit with an error if it can't map\n");
1094 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1095 log(" as final cell types by this mode.\n");
1096 log("\n");
1097 log(" -D <define>, -I <incdir>\n");
1098 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1099 log(" map file. Note that the Verilog frontend is also called with the\n");
1100 log(" '-nooverwrite' option set.\n");
1101 log("\n");
1102 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1103 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1104 log("the module name will be used to match the cell.\n");
1105 log("\n");
1106 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1107 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1108 log("\n");
1109 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1110 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1111 log("\n");
1112 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1113 log("will create a wrapper for the cell and then run the command string that the\n");
1114 log("attribute is set to on the wrapper module.\n");
1115 log("\n");
1116 log("When a port on a module in the map file has the 'techmap_autopurge' attribute\n");
1117 log("set, and that port is not connected in the instantiation that is mapped, then\n");
1118 log("then a cell port connected only to such wires will be omitted in the mapped\n");
1119 log("version of the circuit.\n");
1120 log("\n");
1121 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1122 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1123 log("the mapping module to the techmap command. At the moment the following special\n");
1124 log("wires are supported:\n");
1125 log("\n");
1126 log(" _TECHMAP_FAIL_\n");
1127 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1128 log(" use this module and instead try the next module with a matching\n");
1129 log(" 'techmap_celltype' attribute.\n");
1130 log("\n");
1131 log(" When such a wire exists but does not have a constant value after all\n");
1132 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1133 log("\n");
1134 log(" _TECHMAP_DO_*\n");
1135 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1136 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1137 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1138 log(" that are written using always-statements.\n");
1139 log("\n");
1140 log(" When such a wire has a non-constant value at the time it is to be\n");
1141 log(" evaluated, an error is produced. That means it is possible for such a\n");
1142 log(" wire to start out as non-constant and evaluate to a constant value\n");
1143 log(" during processing of other _TECHMAP_DO_* commands.\n");
1144 log("\n");
1145 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1146 log(" in this case techmap will create a copy for each distinct configuration\n");
1147 log(" of constant inputs and shorted inputs at this point and import the\n");
1148 log(" constant and connected bits into the map module. All further commands\n");
1149 log(" are executed in this copy. This is a very convenient way of creating\n");
1150 log(" optimized specializations of techmap modules without using the special\n");
1151 log(" parameters described below.\n");
1152 log("\n");
1153 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1154 log(" then techmap will recursively replace the cells in the module with their\n");
1155 log(" implementation. This is not affected by the -max_iter option.\n");
1156 log("\n");
1157 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1158 log("\n");
1159 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1160 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1161 log(" connected to this port will be consumed. This wire must have the same\n");
1162 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1163 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1164 log(" bits of an init attribute are left as x, it will be removed.\n");
1165 log("\n");
1166 log("In addition to this special wires, techmap also supports special parameters in\n");
1167 log("modules in the map file:\n");
1168 log("\n");
1169 log(" _TECHMAP_CELLTYPE_\n");
1170 log(" When a parameter with this name exists, it will be set to the type name\n");
1171 log(" of the cell that matches the module.\n");
1172 log("\n");
1173 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1174 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1175 log(" When this pair of parameters is available in a module for a port, then\n");
1176 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1177 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1178 log("\n");
1179 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1180 log(" When a parameter with this name exists, it will be set to the initial\n");
1181 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1182 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1183 log(" missing bits. To remove the init attribute bits used, use the\n");
1184 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1185 log("\n");
1186 log(" _TECHMAP_BITS_CONNMAP_\n");
1187 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1188 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1189 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1190 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1191 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1192 log(" This can be used to detect shorted inputs.\n");
1193 log("\n");
1194 log("When a module in the map file has a parameter where the according cell in the\n");
1195 log("design has a port, the module from the map file is only used if the port in\n");
1196 log("the design is connected to a constant value. The parameter is then set to the\n");
1197 log("constant value.\n");
1198 log("\n");
1199 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1200 log("and attributes of the cell that is being replaced.\n");
1201 log("\n");
1202 log("See 'help extract' for a pass that does the opposite thing.\n");
1203 log("\n");
1204 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1205 log("essentially techmap but using the design itself as map library).\n");
1206 log("\n");
1207 }
1208 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1209 {
1210 log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
1211 log_push();
1212
1213 TechmapWorker worker;
1214 simplemap_get_mappers(worker.simplemap_mappers);
1215
1216 std::vector<std::string> map_files;
1217 std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
1218 int max_iter = -1;
1219
1220 size_t argidx;
1221 for (argidx = 1; argidx < args.size(); argidx++) {
1222 if (args[argidx] == "-map" && argidx+1 < args.size()) {
1223 map_files.push_back(args[++argidx]);
1224 continue;
1225 }
1226 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
1227 max_iter = atoi(args[++argidx].c_str());
1228 continue;
1229 }
1230 if (args[argidx] == "-D" && argidx+1 < args.size()) {
1231 verilog_frontend += " -D " + args[++argidx];
1232 continue;
1233 }
1234 if (args[argidx] == "-I" && argidx+1 < args.size()) {
1235 verilog_frontend += " -I " + args[++argidx];
1236 continue;
1237 }
1238 if (args[argidx] == "-assert") {
1239 worker.assert_mode = true;
1240 continue;
1241 }
1242 if (args[argidx] == "-extern") {
1243 worker.extern_mode = true;
1244 continue;
1245 }
1246 if (args[argidx] == "-recursive") {
1247 worker.recursive_mode = true;
1248 continue;
1249 }
1250 if (args[argidx] == "-autoproc") {
1251 worker.autoproc_mode = true;
1252 continue;
1253 }
1254 if (args[argidx] == "-wb") {
1255 worker.ignore_wb = true;
1256 continue;
1257 }
1258 break;
1259 }
1260 extra_args(args, argidx, design);
1261
1262 RTLIL::Design *map = new RTLIL::Design;
1263 if (map_files.empty()) {
1264 std::istringstream f(stdcells_code);
1265 Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
1266 } else {
1267 for (auto &fn : map_files)
1268 if (fn.compare(0, 1, "%") == 0) {
1269 if (!saved_designs.count(fn.substr(1))) {
1270 delete map;
1271 log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
1272 }
1273 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1274 if (!map->has(mod->name))
1275 map->add(mod->clone());
1276 } else {
1277 std::ifstream f;
1278 rewrite_filename(fn);
1279 f.open(fn.c_str());
1280 yosys_input_files.insert(fn);
1281 if (f.fail())
1282 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
1283 Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
1284 }
1285 }
1286
1287 log_header(design, "Continuing TECHMAP pass.\n");
1288
1289 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1290 for (auto &it : map->modules_) {
1291 if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
1292 char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
1293 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
1294 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
1295 free(p);
1296 } else {
1297 string module_name = it.first.str();
1298 if (it.first.begins_with("\\$"))
1299 module_name = module_name.substr(1);
1300 celltypeMap[module_name].insert(it.first);
1301 }
1302 }
1303
1304 for (auto module : design->modules())
1305 worker.module_queue.insert(module);
1306
1307 while (!worker.module_queue.empty())
1308 {
1309 RTLIL::Module *module = *worker.module_queue.begin();
1310 worker.module_queue.erase(module);
1311
1312 int module_max_iter = max_iter;
1313 bool did_something = true;
1314 std::set<RTLIL::Cell*> handled_cells;
1315 while (did_something) {
1316 did_something = false;
1317 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1318 did_something = true;
1319 if (did_something)
1320 module->check();
1321 if (module_max_iter > 0 && --module_max_iter == 0)
1322 break;
1323 }
1324 }
1325
1326 log("No more expansions possible.\n");
1327 delete map;
1328
1329 log_pop();
1330 }
1331 } TechmapPass;
1332
1333 struct FlattenPass : public Pass {
1334 FlattenPass() : Pass("flatten", "flatten design") { }
1335 void help() YS_OVERRIDE
1336 {
1337 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1338 log("\n");
1339 log(" flatten [options] [selection]\n");
1340 log("\n");
1341 log("This pass flattens the design by replacing cells by their implementation. This\n");
1342 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1343 log("pass is using the current design as mapping library.\n");
1344 log("\n");
1345 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1346 log("flattened by this command.\n");
1347 log("\n");
1348 log(" -wb\n");
1349 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1350 log("\n");
1351 }
1352 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1353 {
1354 log_header(design, "Executing FLATTEN pass (flatten design).\n");
1355 log_push();
1356
1357 TechmapWorker worker;
1358 worker.flatten_mode = true;
1359
1360 size_t argidx;
1361 for (argidx = 1; argidx < args.size(); argidx++) {
1362 if (args[argidx] == "-wb") {
1363 worker.ignore_wb = true;
1364 continue;
1365 }
1366 break;
1367 }
1368 extra_args(args, argidx, design);
1369
1370
1371 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1372 for (auto module : design->modules())
1373 celltypeMap[module->name].insert(module->name);
1374
1375 RTLIL::Module *top_mod = NULL;
1376 if (design->full_selection())
1377 for (auto mod : design->modules())
1378 if (mod->get_bool_attribute(ID(top)))
1379 top_mod = mod;
1380
1381 std::set<RTLIL::Cell*> handled_cells;
1382 if (top_mod != NULL) {
1383 worker.flatten_do_list.insert(top_mod->name);
1384 while (!worker.flatten_do_list.empty()) {
1385 auto mod = design->module(*worker.flatten_do_list.begin());
1386 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1387 worker.flatten_done_list.insert(mod->name);
1388 worker.flatten_do_list.erase(mod->name);
1389 }
1390 } else {
1391 for (auto mod : vector<Module*>(design->modules())) {
1392 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1393 }
1394 }
1395
1396 log_suppressed();
1397 log("No more expansions possible.\n");
1398
1399 if (top_mod != NULL)
1400 {
1401 pool<RTLIL::IdString> used_modules, new_used_modules;
1402 new_used_modules.insert(top_mod->name);
1403 while (!new_used_modules.empty()) {
1404 pool<RTLIL::IdString> queue;
1405 queue.swap(new_used_modules);
1406 for (auto modname : queue)
1407 used_modules.insert(modname);
1408 for (auto modname : queue)
1409 for (auto cell : design->module(modname)->cells())
1410 if (design->module(cell->type) && !used_modules[cell->type])
1411 new_used_modules.insert(cell->type);
1412 }
1413
1414 dict<RTLIL::IdString, RTLIL::Module*> new_modules;
1415 for (auto mod : vector<Module*>(design->modules()))
1416 if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
1417 new_modules[mod->name] = mod;
1418 } else {
1419 log("Deleting now unused module %s.\n", log_id(mod));
1420 delete mod;
1421 }
1422 design->modules_.swap(new_modules);
1423 }
1424
1425 log_pop();
1426 }
1427 } FlattenPass;
1428
1429 PRIVATE_NAMESPACE_END