projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Added topological sorting to techmap
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/toposort.h"
24 #include "kernel/log.h"
25 #include <stdlib.h>
26 #include <assert.h>
27 #include <stdio.h>
28 #include <string.h>
29
30 #include "passes/techmap/stdcells.inc"
31
32 // see simplemap.cc
33 extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
34
35 static void apply_prefix(std::string prefix, std::string &id)
36 {
37 if (id[0] == '\\')
38 id = prefix + "." + id.substr(1);
39 else
40 id = "$techmap" + prefix + "." + id;
41 }
42
43 static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
44 {
45 std::vector<RTLIL::SigChunk> chunks = sig;
46 for (auto &chunk : chunks)
47 if (chunk.wire != NULL) {
48 std::string wire_name = chunk.wire->name;
49 apply_prefix(prefix, wire_name);
50 assert(module->wires_.count(wire_name) > 0);
51 chunk.wire = module->wires_[wire_name];
52 }
53 sig = chunks;
54 }
55
56 struct TechmapWorker
57 {
58 std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
59 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
60 std::map<RTLIL::Module*, bool> techmap_do_cache;
61
62 struct TechmapWireData {
63 RTLIL::Wire *wire;
64 RTLIL::SigSpec value;
65 };
66
67 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
68
69 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
70 {
71 TechmapWires result;
72
73 if (module == NULL)
74 return result;
75
76 for (auto &it : module->wires_) {
77 const char *p = it.first.c_str();
78 if (*p == '$')
79 continue;
80
81 const char *q = strrchr(p+1, '.');
82 p = q ? q : p+1;
83
84 if (!strncmp(p, "_TECHMAP_", 9)) {
85 TechmapWireData record;
86 record.wire = it.second;
87 record.value = it.second;
88 result[p].push_back(record);
89 it.second->attributes["\\keep"] = RTLIL::Const(1);
90 it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
91 }
92 }
93
94 if (!result.empty()) {
95 SigMap sigmap(module);
96 for (auto &it1 : result)
97 for (auto &it2 : it1.second)
98 sigmap.apply(it2.value);
99 }
100
101 return result;
102 }
103
104 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
105 {
106 log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
107
108 if (tpl->memories.size() != 0)
109 log_error("Technology map yielded memories -> this is not supported.\n");
110
111 if (tpl->processes.size() != 0) {
112 log("Technology map yielded processes:\n");
113 for (auto &it : tpl->processes)
114 log(" %s",RTLIL::id2cstr(it.first));
115 log_error("Technology map yielded processes -> this is not supported.\n");
116 }
117
118 std::string orig_cell_name;
119 if (!flatten_mode)
120 for (auto &it : tpl->cells_)
121 if (it.first == "\\_TECHMAP_REPLACE_") {
122 orig_cell_name = cell->name;
123 module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
124 break;
125 }
126
127 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
128
129 for (auto &it : tpl->wires_) {
130 if (it.second->port_id > 0)
131 positional_ports[stringf("$%d", it.second->port_id)] = it.first;
132 std::string w_name = it.second->name;
133 apply_prefix(cell->name, w_name);
134 RTLIL::Wire *w = module->addWire(w_name, it.second);
135 w->port_input = false;
136 w->port_output = false;
137 w->port_id = 0;
138 if (it.second->get_bool_attribute("\\_techmap_special_"))
139 w->attributes.clear();
140 design->select(module, w);
141 }
142
143 SigMap port_signal_map;
144
145 for (auto &it : cell->connections()) {
146 RTLIL::IdString portname = it.first;
147 if (positional_ports.count(portname) > 0)
148 portname = positional_ports.at(portname);
149 if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
150 if (portname.substr(0, 1) == "$")
151 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
152 continue;
153 }
154 RTLIL::Wire *w = tpl->wires_.at(portname);
155 RTLIL::SigSig c;
156 if (w->port_output) {
157 c.first = it.second;
158 c.second = RTLIL::SigSpec(w);
159 apply_prefix(cell->name, c.second, module);
160 } else {
161 c.first = RTLIL::SigSpec(w);
162 c.second = it.second;
163 apply_prefix(cell->name, c.first, module);
164 }
165 if (c.second.size() > c.first.size())
166 c.second.remove(c.first.size(), c.second.size() - c.first.size());
167 if (c.second.size() < c.first.size())
168 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
169 assert(c.first.size() == c.second.size());
170 if (flatten_mode) {
171 // more conservative approach:
172 // connect internal and external wires
173 module->connect(c);
174 } else {
175 // approach that yields nicer outputs:
176 // replace internal wires that are connected to external wires
177 if (w->port_output)
178 port_signal_map.add(c.second, c.first);
179 else
180 port_signal_map.add(c.first, c.second);
181 }
182 }
183
184 for (auto &it : tpl->cells_)
185 {
186 RTLIL::IdString c_name = it.second->name;
187
188 if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
189 c_name = orig_cell_name;
190 else
191 apply_prefix(cell->name, c_name);
192
193 RTLIL::Cell *c = module->addCell(c_name, it.second);
194 design->select(module, c);
195
196 if (!flatten_mode && c->type.substr(0, 2) == "\\$")
197 c->type = c->type.substr(1);
198
199 for (auto &it2 : c->connections_) {
200 apply_prefix(cell->name, it2.second, module);
201 port_signal_map.apply(it2.second);
202 }
203 }
204
205 for (auto &it : tpl->connections()) {
206 RTLIL::SigSig c = it;
207 apply_prefix(cell->name, c.first, module);
208 apply_prefix(cell->name, c.second, module);
209 port_signal_map.apply(c.first);
210 port_signal_map.apply(c.second);
211 module->connect(c);
212 }
213
214 module->remove(cell);
215 }
216
217 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
218 const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
219 {
220 if (!design->selected(module))
221 return false;
222
223 bool log_continue = false;
224 bool did_something = false;
225
226 SigMap sigmap(module);
227
228 TopoSort<RTLIL::Cell*> cells;
229 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
230 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
231
232 for (auto cell : module->cells())
233 {
234 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
235 continue;
236
237 if (celltypeMap.count(cell->type) == 0)
238 continue;
239
240 for (auto &conn : cell->connections())
241 {
242 RTLIL::SigSpec sig = sigmap(conn.second);
243 sig.remove_const();
244
245 if (SIZE(sig) == 0)
246 continue;
247
248 for (auto &tpl_name : celltypeMap.at(cell->type)) {
249 RTLIL::Module *tpl = map->modules_[tpl_name];
250 RTLIL::Wire *port = tpl->wire(conn.first);
251 if (port && port->port_input)
252 cell_to_inbit[cell].insert(sig.begin(), sig.end());
253 if (port && port->port_output)
254 for (auto &bit : sig)
255 outbit_to_cell[bit].insert(cell);
256 }
257 }
258
259 cells.node(cell);
260 }
261
262 for (auto &it_right : cell_to_inbit)
263 for (auto &it_sigbit : it_right.second)
264 for (auto &it_left : outbit_to_cell[it_sigbit])
265 cells.edge(it_left, it_right.first);
266
267 cells.sort();
268
269 for (auto cell : cells.sorted)
270 {
271 log_assert(handled_cells.count(cell) == 0);
272 log_assert(cell == module->cell(cell->name));
273
274 for (auto &tpl_name : celltypeMap.at(cell->type))
275 {
276 std::string derived_name = tpl_name;
277 RTLIL::Module *tpl = map->modules_[tpl_name];
278 std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
279
280 if (tpl->get_bool_attribute("\\blackbox"))
281 continue;
282
283 if (!flatten_mode)
284 {
285 if (tpl->get_bool_attribute("\\techmap_simplemap")) {
286 log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
287 if (simplemap_mappers.count(cell->type) == 0)
288 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
289 simplemap_mappers.at(cell->type)(module, cell);
290 module->remove(cell);
291 cell = NULL;
292 did_something = true;
293 break;
294 }
295
296 for (auto conn : cell->connections()) {
297 if (conn.first.substr(0, 1) == "$")
298 continue;
299 if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
300 continue;
301 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
302 goto next_tpl;
303 parameters[conn.first] = conn.second.as_const();
304 }
305
306 if (0) {
307 next_tpl:
308 continue;
309 }
310
311 if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
312 parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
313
314 for (auto conn : cell->connections()) {
315 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
316 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
317 for (auto &bit : v)
318 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
319 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
320 }
321 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
322 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
323 for (auto &bit : v)
324 if (bit.wire != NULL)
325 bit = RTLIL::SigBit(RTLIL::State::Sx);
326 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
327 }
328 }
329
330 int unique_bit_id_counter = 0;
331 std::map<RTLIL::SigBit, int> unique_bit_id;
332 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
333 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
334 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
335 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
336
337 for (auto conn : cell->connections())
338 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
339 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
340 if (unique_bit_id.count(bit) == 0)
341 unique_bit_id[bit] = unique_bit_id_counter++;
342 }
343
344 int bits = 0;
345 for (int i = 0; i < 32; i++)
346 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
347 bits = i;
348 if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
349 parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
350
351 for (auto conn : cell->connections())
352 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
353 RTLIL::Const value;
354 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
355 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
356 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
357 }
358 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
359 }
360 }
361
362 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
363 if (techmap_cache.count(key) > 0) {
364 tpl = techmap_cache[key];
365 } else {
366 if (cell->parameters.size() != 0) {
367 derived_name = tpl->derive(map, parameters);
368 tpl = map->modules_[derived_name];
369 log_continue = true;
370 }
371 techmap_cache[key] = tpl;
372 }
373
374 if (flatten_mode)
375 techmap_do_cache[tpl] = true;
376
377 if (techmap_do_cache.count(tpl) == 0)
378 {
379 bool keep_running = true;
380 techmap_do_cache[tpl] = true;
381
382 std::set<std::string> techmap_wire_names;
383
384 while (keep_running)
385 {
386 TechmapWires twd = techmap_find_special_wires(tpl);
387 keep_running = false;
388
389 for (auto &it : twd)
390 techmap_wire_names.insert(it.first);
391
392 for (auto &it : twd["_TECHMAP_FAIL_"]) {
393 RTLIL::SigSpec value = it.value;
394 if (value.is_fully_const() && value.as_bool()) {
395 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
396 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
397 techmap_do_cache[tpl] = false;
398 }
399 }
400
401 if (!techmap_do_cache[tpl])
402 break;
403
404 for (auto &it : twd)
405 {
406 if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
407 continue;
408
409 auto &data = it.second.front();
410
411 if (!data.value.is_fully_const())
412 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
413
414 techmap_wire_names.erase(it.first);
415
416 const char *p = data.wire->name.c_str();
417 const char *q = strrchr(p+1, '.');
418 q = q ? q : p+1;
419
420 assert(!strncmp(q, "_TECHMAP_DO_", 12));
421 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
422 while (tpl->wires_.count(new_name))
423 new_name += "_";
424 tpl->rename(data.wire, new_name);
425
426 std::string cmd_string = data.value.as_const().decode_string();
427 Pass::call_on_module(map, tpl, cmd_string);
428
429 keep_running = true;
430 break;
431 }
432 }
433
434 TechmapWires twd = techmap_find_special_wires(tpl);
435 for (auto &it : twd) {
436 if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
437 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
438 if (techmap_do_cache[tpl])
439 for (auto &it2 : it.second)
440 if (!it2.value.is_fully_const())
441 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
442 techmap_wire_names.erase(it.first);
443 }
444
445 for (auto &it : techmap_wire_names)
446 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
447 }
448
449 if (techmap_do_cache.at(tpl) == false)
450 continue;
451
452 if (log_continue) {
453 log_header("Continuing TECHMAP pass.\n");
454 log_continue = false;
455 }
456
457 techmap_module_worker(design, module, cell, tpl, flatten_mode);
458 did_something = true;
459 cell = NULL;
460 break;
461 }
462
463 handled_cells.insert(cell);
464 }
465
466 if (log_continue) {
467 log_header("Continuing TECHMAP pass.\n");
468 log_continue = false;
469 }
470
471 return did_something;
472 }
473 };
474
475 struct TechmapPass : public Pass {
476 TechmapPass() : Pass("techmap", "generic technology mapper") { }
477 virtual void help()
478 {
479 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
480 log("\n");
481 log(" techmap [-map filename] [selection]\n");
482 log("\n");
483 log("This pass implements a very simple technology mapper that replaces cells in\n");
484 log("the design with implementations given in form of a verilog or ilang source\n");
485 log("file.\n");
486 log("\n");
487 log(" -map filename\n");
488 log(" the library of cell implementations to be used.\n");
489 log(" without this parameter a builtin library is used that\n");
490 log(" transforms the internal RTL cells to the internal gate\n");
491 log(" library.\n");
492 log("\n");
493 log(" -share_map filename\n");
494 log(" like -map, but look for the file in the share directory (where the\n");
495 log(" yosys data files are). this is mainly used internally when techmap\n");
496 log(" is called from other commands.\n");
497 log("\n");
498 log(" -max_iter <number>\n");
499 log(" only run the specified number of iterations.\n");
500 log("\n");
501 log(" -D <define>, -I <incdir>\n");
502 log(" this options are passed as-is to the verilog frontend for loading the\n");
503 log(" map file. Note that the verilog frontend is also called with the\n");
504 log(" '-ignore_redef' option set.\n");
505 log("\n");
506 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
507 log("match cells with a type that match the text value of this attribute. Otherwise\n");
508 log("the module name will be used to match the cell.\n");
509 log("\n");
510 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
511 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
512 log("\n");
513 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
514 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
515 log("the mapping module to the techmap command. At the moment the following special\n");
516 log("wires are supported:\n");
517 log("\n");
518 log(" _TECHMAP_FAIL_\n");
519 log(" When this wire is set to a non-zero constant value, techmap will not\n");
520 log(" use this module and instead try the next module with a matching\n");
521 log(" 'techmap_celltype' attribute.\n");
522 log("\n");
523 log(" When such a wire exists but does not have a constant value after all\n");
524 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
525 log("\n");
526 log(" _TECHMAP_DO_*\n");
527 log(" This wires are evaluated in alphabetical order. The constant text value\n");
528 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
529 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
530 log(" that are written using always-statements.\n");
531 log("\n");
532 log(" When such a wire has a non-constant value at the time it is to be\n");
533 log(" evaluated, an error is produced. That means it is possible for such a\n");
534 log(" wire to start out as non-constant and evaluate to a constant value\n");
535 log(" during processing of other _TECHMAP_DO_* commands.\n");
536 log("\n");
537 log("In addition to this special wires, techmap also supports special parameters in\n");
538 log("modules in the map file:\n");
539 log("\n");
540 log(" _TECHMAP_CELLTYPE_\n");
541 log(" When a parameter with this name exists, it will be set to the type name\n");
542 log(" of the cell that matches the module.\n");
543 log("\n");
544 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
545 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
546 log(" When this pair of parameters is available in a module for a port, then\n");
547 log(" former has a 1-bit for each constant input bit and the latter has the\n");
548 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
549 log("\n");
550 log(" _TECHMAP_BITS_CONNMAP_\n");
551 log(" _TECHMAP_CONNMAP_<port-name>_\n");
552 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
553 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
554 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
555 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
556 log(" This can be used to detect shorted inputs.\n");
557 log("\n");
558 log("When a module in the map file has a parameter where the according cell in the\n");
559 log("design has a port, the module from the map file is only used if the port in\n");
560 log("the design is connected to a constant value. The parameter is then set to the\n");
561 log("constant value.\n");
562 log("\n");
563 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
564 log("of the cell that is beeing replaced.\n");
565 log("\n");
566 log("See 'help extract' for a pass that does the opposite thing.\n");
567 log("\n");
568 log("See 'help flatten' for a pass that does flatten the design (which is\n");
569 log("esentially techmap but using the design itself as map library).\n");
570 log("\n");
571 }
572 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
573 {
574 log_header("Executing TECHMAP pass (map to technology primitives).\n");
575 log_push();
576
577 std::vector<std::string> map_files;
578 std::string verilog_frontend = "verilog -ignore_redef";
579 int max_iter = -1;
580
581 size_t argidx;
582 std::string proc_share_path = proc_share_dirname();
583 for (argidx = 1; argidx < args.size(); argidx++) {
584 if (args[argidx] == "-map" && argidx+1 < args.size()) {
585 map_files.push_back(args[++argidx]);
586 continue;
587 }
588 if (args[argidx] == "-share_map" && argidx+1 < args.size()) {
589 map_files.push_back(proc_share_path + args[++argidx]);
590 continue;
591 }
592 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
593 max_iter = atoi(args[++argidx].c_str());
594 continue;
595 }
596 if (args[argidx] == "-D" && argidx+1 < args.size()) {
597 verilog_frontend += " -D " + args[++argidx];
598 continue;
599 }
600 if (args[argidx] == "-I" && argidx+1 < args.size()) {
601 verilog_frontend += " -I " + args[++argidx];
602 continue;
603 }
604 break;
605 }
606 extra_args(args, argidx, design);
607
608 TechmapWorker worker;
609 simplemap_get_mappers(worker.simplemap_mappers);
610
611 RTLIL::Design *map = new RTLIL::Design;
612 if (map_files.empty()) {
613 FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
614 Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
615 fclose(f);
616 } else
617 for (auto &fn : map_files) {
618 FILE *f = fopen(fn.c_str(), "rt");
619 if (f == NULL)
620 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
621 Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
622 fclose(f);
623 }
624
625 std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
626 for (auto &it : map->modules_) {
627 if (it.first.substr(0, 2) == "\\$")
628 it.second->name = it.first.substr(1);
629 modules_new[it.second->name] = it.second;
630 }
631 map->modules_.swap(modules_new);
632
633 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
634 for (auto &it : map->modules_) {
635 if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
636 char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
637 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
638 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
639 free(p);
640 } else
641 celltypeMap[it.first].insert(it.first);
642 }
643
644 for (auto module : design->modules()) {
645 bool did_something = true;
646 std::set<RTLIL::Cell*> handled_cells;
647 while (did_something) {
648 did_something = false;
649 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
650 did_something = true;
651 if (did_something)
652 module->check();
653 if (max_iter > 0 && --max_iter == 0)
654 break;
655 }
656 }
657
658 log("No more expansions possible.\n");
659 delete map;
660
661 log_pop();
662 }
663 } TechmapPass;
664
665 struct FlattenPass : public Pass {
666 FlattenPass() : Pass("flatten", "flatten design") { }
667 virtual void help()
668 {
669 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
670 log("\n");
671 log(" flatten [selection]\n");
672 log("\n");
673 log("This pass flattens the design by replacing cells by their implementation. This\n");
674 log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
675 log("pass is using the current design as mapping library.\n");
676 log("\n");
677 }
678 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
679 {
680 log_header("Executing FLATTEN pass (flatten design).\n");
681 log_push();
682
683 extra_args(args, 1, design);
684
685 TechmapWorker worker;
686
687 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
688 for (auto &it : design->modules_)
689 celltypeMap[it.first].insert(it.first);
690
691 RTLIL::Module *top_mod = NULL;
692 if (design->full_selection())
693 for (auto mod : design->modules())
694 if (mod->get_bool_attribute("\\top"))
695 top_mod = mod;
696
697 bool did_something = true;
698 std::set<RTLIL::Cell*> handled_cells;
699 while (did_something) {
700 did_something = false;
701 if (top_mod != NULL) {
702 if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
703 did_something = true;
704 } else {
705 for (auto mod : design->modules())
706 if (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, true))
707 did_something = true;
708 }
709 }
710
711 log("No more expansions possible.\n");
712
713 if (top_mod != NULL) {
714 std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
715 for (auto mod : design->modules())
716 if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) {
717 new_modules[mod->name] = mod;
718 } else {
719 log("Deleting now unused module %s.\n", log_id(mod));
720 delete mod;
721 }
722 design->modules_.swap(new_modules);
723 }
724
725 log_pop();
726 }
727 } FlattenPass;
728