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SigSpec refactoring: renamed chunks and width to __chunks and __width
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/compatibility.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/log.h"
24 #include <stdlib.h>
25 #include <assert.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "passes/techmap/stdcells.inc"
30
31 // see simplemap.cc
32 extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
33
34 static void apply_prefix(std::string prefix, std::string &id)
35 {
36 if (id[0] == '\\')
37 id = prefix + "." + id.substr(1);
38 else
39 id = "$techmap" + prefix + "." + id;
40 }
41
42 static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
43 {
44 for (size_t i = 0; i < sig.__chunks.size(); i++) {
45 if (sig.__chunks[i].wire == NULL)
46 continue;
47 std::string wire_name = sig.__chunks[i].wire->name;
48 apply_prefix(prefix, wire_name);
49 assert(module->wires.count(wire_name) > 0);
50 sig.__chunks[i].wire = module->wires[wire_name];
51 }
52 }
53
54 struct TechmapWorker
55 {
56 std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
57 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
58 std::map<RTLIL::Module*, bool> techmap_do_cache;
59
60 struct TechmapWireData {
61 RTLIL::Wire *wire;
62 RTLIL::SigSpec value;
63 };
64
65 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
66
67 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
68 {
69 TechmapWires result;
70
71 if (module == NULL)
72 return result;
73
74 for (auto &it : module->wires) {
75 const char *p = it.first.c_str();
76 if (*p == '$')
77 continue;
78
79 const char *q = strrchr(p+1, '.');
80 p = q ? q : p+1;
81
82 if (!strncmp(p, "_TECHMAP_", 9)) {
83 TechmapWireData record;
84 record.wire = it.second;
85 record.value = it.second;
86 result[p].push_back(record);
87 it.second->attributes["\\keep"] = RTLIL::Const(1);
88 it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
89 }
90 }
91
92 if (!result.empty()) {
93 SigMap sigmap(module);
94 for (auto &it1 : result)
95 for (auto &it2 : it1.second)
96 sigmap.apply(it2.value);
97 }
98
99 return result;
100 }
101
102 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
103 {
104 log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
105
106 if (tpl->memories.size() != 0)
107 log_error("Technology map yielded memories -> this is not supported.\n");
108
109 if (tpl->processes.size() != 0) {
110 log("Technology map yielded processes:\n");
111 for (auto &it : tpl->processes)
112 log(" %s",RTLIL::id2cstr(it.first));
113 log_error("Technology map yielded processes -> this is not supported.\n");
114 }
115
116 // erase from namespace first for _TECHMAP_REPLACE_ to work
117 module->cells.erase(cell->name);
118 std::string orig_cell_name;
119
120 if (!flatten_mode)
121 for (auto &it : tpl->cells)
122 if (it.first == "\\_TECHMAP_REPLACE_") {
123 orig_cell_name = cell->name;
124 cell->name = stringf("$techmap%d", RTLIL::autoidx++) + cell->name;
125 break;
126 }
127
128 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
129
130 for (auto &it : tpl->wires) {
131 if (it.second->port_id > 0)
132 positional_ports[stringf("$%d", it.second->port_id)] = it.first;
133 RTLIL::Wire *w = new RTLIL::Wire(*it.second);
134 apply_prefix(cell->name, w->name);
135 w->port_input = false;
136 w->port_output = false;
137 w->port_id = 0;
138 if (it.second->get_bool_attribute("\\_techmap_special_"))
139 w->attributes.clear();
140 module->add(w);
141 design->select(module, w);
142 }
143
144 SigMap port_signal_map;
145
146 for (auto &it : cell->connections) {
147 RTLIL::IdString portname = it.first;
148 if (positional_ports.count(portname) > 0)
149 portname = positional_ports.at(portname);
150 if (tpl->wires.count(portname) == 0 || tpl->wires.at(portname)->port_id == 0) {
151 if (portname.substr(0, 1) == "$")
152 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
153 continue;
154 }
155 RTLIL::Wire *w = tpl->wires.at(portname);
156 RTLIL::SigSig c;
157 if (w->port_output) {
158 c.first = it.second;
159 c.second = RTLIL::SigSpec(w);
160 apply_prefix(cell->name, c.second, module);
161 } else {
162 c.first = RTLIL::SigSpec(w);
163 c.second = it.second;
164 apply_prefix(cell->name, c.first, module);
165 }
166 if (c.second.__width > c.first.__width)
167 c.second.remove(c.first.__width, c.second.__width - c.first.__width);
168 if (c.second.__width < c.first.__width)
169 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.__width - c.second.__width));
170 assert(c.first.__width == c.second.__width);
171 if (flatten_mode) {
172 // more conservative approach:
173 // connect internal and external wires
174 module->connections.push_back(c);
175 } else {
176 // approach that yields nicer outputs:
177 // replace internal wires that are connected to external wires
178 if (w->port_output)
179 port_signal_map.add(c.second, c.first);
180 else
181 port_signal_map.add(c.first, c.second);
182 }
183 }
184
185 for (auto &it : tpl->cells) {
186 RTLIL::Cell *c = new RTLIL::Cell(*it.second);
187 if (!flatten_mode && c->type.substr(0, 2) == "\\$")
188 c->type = c->type.substr(1);
189 if (!flatten_mode && c->name == "\\_TECHMAP_REPLACE_")
190 c->name = orig_cell_name;
191 else
192 apply_prefix(cell->name, c->name);
193 for (auto &it2 : c->connections) {
194 apply_prefix(cell->name, it2.second, module);
195 port_signal_map.apply(it2.second);
196 }
197 module->add(c);
198 design->select(module, c);
199 }
200
201 for (auto &it : tpl->connections) {
202 RTLIL::SigSig c = it;
203 apply_prefix(cell->name, c.first, module);
204 apply_prefix(cell->name, c.second, module);
205 port_signal_map.apply(c.first);
206 port_signal_map.apply(c.second);
207 module->connections.push_back(c);
208 }
209
210 delete cell;
211 }
212
213 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
214 const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
215 {
216 if (!design->selected(module))
217 return false;
218
219 bool log_continue = false;
220 bool did_something = false;
221 std::vector<std::string> cell_names;
222
223 SigMap sigmap(module);
224 for (auto &cell_it : module->cells)
225 cell_names.push_back(cell_it.first);
226
227 for (auto &cell_name : cell_names)
228 {
229 if (module->cells.count(cell_name) == 0)
230 continue;
231
232 RTLIL::Cell *cell = module->cells[cell_name];
233
234 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
235 continue;
236
237 if (celltypeMap.count(cell->type) == 0)
238 continue;
239
240 for (auto &tpl_name : celltypeMap.at(cell->type))
241 {
242 std::string derived_name = tpl_name;
243 RTLIL::Module *tpl = map->modules[tpl_name];
244 std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
245
246 if (tpl->get_bool_attribute("\\blackbox"))
247 continue;
248
249 if (!flatten_mode)
250 {
251 if (tpl->get_bool_attribute("\\techmap_simplemap")) {
252 log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
253 if (simplemap_mappers.count(cell->type) == 0)
254 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
255 simplemap_mappers.at(cell->type)(module, cell);
256 module->cells.erase(cell->name);
257 delete cell;
258 cell = NULL;
259 did_something = true;
260 break;
261 }
262
263 for (auto conn : cell->connections) {
264 if (conn.first.substr(0, 1) == "$")
265 continue;
266 if (tpl->wires.count(conn.first) > 0 && tpl->wires.at(conn.first)->port_id > 0)
267 continue;
268 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
269 goto next_tpl;
270 parameters[conn.first] = conn.second.as_const();
271 }
272
273 if (0) {
274 next_tpl:
275 continue;
276 }
277
278 if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
279 parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
280
281 for (auto conn : cell->connections) {
282 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
283 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
284 for (auto &bit : v)
285 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
286 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
287 }
288 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
289 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
290 for (auto &bit : v)
291 if (bit.wire != NULL)
292 bit = RTLIL::SigBit(RTLIL::State::Sx);
293 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
294 }
295 }
296
297 int unique_bit_id_counter = 0;
298 std::map<RTLIL::SigBit, int> unique_bit_id;
299 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
300 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
301 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
302 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
303
304 for (auto conn : cell->connections)
305 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
306 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
307 if (unique_bit_id.count(bit) == 0)
308 unique_bit_id[bit] = unique_bit_id_counter++;
309 }
310
311 int bits = 0;
312 for (int i = 0; i < 32; i++)
313 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
314 bits = i;
315 if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
316 parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
317
318 for (auto conn : cell->connections)
319 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
320 RTLIL::Const value;
321 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
322 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
323 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
324 }
325 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
326 }
327 }
328
329 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
330 if (techmap_cache.count(key) > 0) {
331 tpl = techmap_cache[key];
332 } else {
333 if (cell->parameters.size() != 0) {
334 derived_name = tpl->derive(map, parameters);
335 tpl = map->modules[derived_name];
336 log_continue = true;
337 }
338 techmap_cache[key] = tpl;
339 }
340
341 if (flatten_mode)
342 techmap_do_cache[tpl] = true;
343
344 if (techmap_do_cache.count(tpl) == 0)
345 {
346 bool keep_running = true;
347 techmap_do_cache[tpl] = true;
348
349 std::set<std::string> techmap_wire_names;
350
351 while (keep_running)
352 {
353 TechmapWires twd = techmap_find_special_wires(tpl);
354 keep_running = false;
355
356 for (auto &it : twd)
357 techmap_wire_names.insert(it.first);
358
359 for (auto &it : twd["_TECHMAP_FAIL_"]) {
360 RTLIL::SigSpec value = it.value;
361 if (value.is_fully_const() && value.as_bool()) {
362 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
363 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
364 techmap_do_cache[tpl] = false;
365 }
366 }
367
368 if (!techmap_do_cache[tpl])
369 break;
370
371 for (auto &it : twd)
372 {
373 if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
374 continue;
375
376 auto &data = it.second.front();
377
378 if (!data.value.is_fully_const())
379 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
380
381 techmap_wire_names.erase(it.first);
382 tpl->wires.erase(data.wire->name);
383
384 const char *p = data.wire->name.c_str();
385 const char *q = strrchr(p+1, '.');
386 q = q ? q : p+1;
387
388 assert(!strncmp(q, "_TECHMAP_DO_", 12));
389 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
390 while (tpl->wires.count(new_name))
391 new_name += "_";
392 data.wire->name = new_name;
393 tpl->add(data.wire);
394
395 std::string cmd_string = data.value.as_const().decode_string();
396 Pass::call_on_module(map, tpl, cmd_string);
397
398 keep_running = true;
399 break;
400 }
401 }
402
403 TechmapWires twd = techmap_find_special_wires(tpl);
404 for (auto &it : twd) {
405 if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
406 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
407 if (techmap_do_cache[tpl])
408 for (auto &it2 : it.second)
409 if (!it2.value.is_fully_const())
410 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
411 techmap_wire_names.erase(it.first);
412 }
413
414 for (auto &it : techmap_wire_names)
415 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
416 }
417
418 if (techmap_do_cache.at(tpl) == false)
419 continue;
420
421 if (log_continue) {
422 log_header("Continuing TECHMAP pass.\n");
423 log_continue = false;
424 }
425
426 techmap_module_worker(design, module, cell, tpl, flatten_mode);
427 did_something = true;
428 cell = NULL;
429 break;
430 }
431
432 handled_cells.insert(cell);
433 }
434
435 if (log_continue) {
436 log_header("Continuing TECHMAP pass.\n");
437 log_continue = false;
438 }
439
440 return did_something;
441 }
442 };
443
444 struct TechmapPass : public Pass {
445 TechmapPass() : Pass("techmap", "generic technology mapper") { }
446 virtual void help()
447 {
448 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
449 log("\n");
450 log(" techmap [-map filename] [selection]\n");
451 log("\n");
452 log("This pass implements a very simple technology mapper that replaces cells in\n");
453 log("the design with implementations given in form of a verilog or ilang source\n");
454 log("file.\n");
455 log("\n");
456 log(" -map filename\n");
457 log(" the library of cell implementations to be used.\n");
458 log(" without this parameter a builtin library is used that\n");
459 log(" transforms the internal RTL cells to the internal gate\n");
460 log(" library.\n");
461 log("\n");
462 log(" -share_map filename\n");
463 log(" like -map, but look for the file in the share directory (where the\n");
464 log(" yosys data files are). this is mainly used internally when techmap\n");
465 log(" is called from other commands.\n");
466 log("\n");
467 log(" -max_iter <number>\n");
468 log(" only run the specified number of iterations.\n");
469 log("\n");
470 log(" -D <define>, -I <incdir>\n");
471 log(" this options are passed as-is to the verilog frontend for loading the\n");
472 log(" map file. Note that the verilog frontend is also called with the\n");
473 log(" '-ignore_redef' option set.\n");
474 log("\n");
475 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
476 log("match cells with a type that match the text value of this attribute. Otherwise\n");
477 log("the module name will be used to match the cell.\n");
478 log("\n");
479 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
480 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
481 log("\n");
482 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
483 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
484 log("the mapping module to the techmap command. At the moment the following special\n");
485 log("wires are supported:\n");
486 log("\n");
487 log(" _TECHMAP_FAIL_\n");
488 log(" When this wire is set to a non-zero constant value, techmap will not\n");
489 log(" use this module and instead try the next module with a matching\n");
490 log(" 'techmap_celltype' attribute.\n");
491 log("\n");
492 log(" When such a wire exists but does not have a constant value after all\n");
493 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
494 log("\n");
495 log(" _TECHMAP_DO_*\n");
496 log(" This wires are evaluated in alphabetical order. The constant text value\n");
497 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
498 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
499 log(" that are written using always-statements.\n");
500 log("\n");
501 log(" When such a wire has a non-constant value at the time it is to be\n");
502 log(" evaluated, an error is produced. That means it is possible for such a\n");
503 log(" wire to start out as non-constant and evaluate to a constant value\n");
504 log(" during processing of other _TECHMAP_DO_* commands.\n");
505 log("\n");
506 log("In addition to this special wires, techmap also supports special parameters in\n");
507 log("modules in the map file:\n");
508 log("\n");
509 log(" _TECHMAP_CELLTYPE_\n");
510 log(" When a parameter with this name exists, it will be set to the type name\n");
511 log(" of the cell that matches the module.\n");
512 log("\n");
513 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
514 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
515 log(" When this pair of parameters is available in a module for a port, then\n");
516 log(" former has a 1-bit for each constant input bit and the latter has the\n");
517 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
518 log("\n");
519 log(" _TECHMAP_BITS_CONNMAP_\n");
520 log(" _TECHMAP_CONNMAP_<port-name>_\n");
521 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
522 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
523 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
524 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
525 log(" This can be used to detect shorted inputs.\n");
526 log("\n");
527 log("When a module in the map file has a parameter where the according cell in the\n");
528 log("design has a port, the module from the map file is only used if the port in\n");
529 log("the design is connected to a constant value. The parameter is then set to the\n");
530 log("constant value.\n");
531 log("\n");
532 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
533 log("of the cell that is beeing replaced.\n");
534 log("\n");
535 log("See 'help extract' for a pass that does the opposite thing.\n");
536 log("\n");
537 log("See 'help flatten' for a pass that does flatten the design (which is\n");
538 log("esentially techmap but using the design itself as map library).\n");
539 log("\n");
540 }
541 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
542 {
543 log_header("Executing TECHMAP pass (map to technology primitives).\n");
544 log_push();
545
546 std::vector<std::string> map_files;
547 std::string verilog_frontend = "verilog -ignore_redef";
548 int max_iter = -1;
549
550 size_t argidx;
551 std::string proc_share_path = proc_share_dirname();
552 for (argidx = 1; argidx < args.size(); argidx++) {
553 if (args[argidx] == "-map" && argidx+1 < args.size()) {
554 map_files.push_back(args[++argidx]);
555 continue;
556 }
557 if (args[argidx] == "-share_map" && argidx+1 < args.size()) {
558 map_files.push_back(proc_share_path + args[++argidx]);
559 continue;
560 }
561 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
562 max_iter = atoi(args[++argidx].c_str());
563 continue;
564 }
565 if (args[argidx] == "-D" && argidx+1 < args.size()) {
566 verilog_frontend += " -D " + args[++argidx];
567 continue;
568 }
569 if (args[argidx] == "-I" && argidx+1 < args.size()) {
570 verilog_frontend += " -I " + args[++argidx];
571 continue;
572 }
573 break;
574 }
575 extra_args(args, argidx, design);
576
577 TechmapWorker worker;
578 simplemap_get_mappers(worker.simplemap_mappers);
579
580 RTLIL::Design *map = new RTLIL::Design;
581 if (map_files.empty()) {
582 FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
583 Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
584 fclose(f);
585 } else
586 for (auto &fn : map_files) {
587 FILE *f = fopen(fn.c_str(), "rt");
588 if (f == NULL)
589 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
590 Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
591 fclose(f);
592 }
593
594 std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
595 for (auto &it : map->modules) {
596 if (it.first.substr(0, 2) == "\\$")
597 it.second->name = it.first.substr(1);
598 modules_new[it.second->name] = it.second;
599 }
600 map->modules.swap(modules_new);
601
602 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
603 for (auto &it : map->modules) {
604 if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
605 char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
606 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
607 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
608 free(p);
609 } else
610 celltypeMap[it.first].insert(it.first);
611 }
612
613 bool did_something = true;
614 std::set<RTLIL::Cell*> handled_cells;
615 while (did_something) {
616 did_something = false;
617 for (auto &mod_it : design->modules)
618 if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
619 did_something = true;
620 if (did_something)
621 design->check();
622 if (max_iter > 0 && --max_iter == 0)
623 break;
624 }
625
626 log("No more expansions possible.\n");
627 delete map;
628
629 log_pop();
630 }
631 } TechmapPass;
632
633 struct FlattenPass : public Pass {
634 FlattenPass() : Pass("flatten", "flatten design") { }
635 virtual void help()
636 {
637 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
638 log("\n");
639 log(" flatten [selection]\n");
640 log("\n");
641 log("This pass flattens the design by replacing cells by their implementation. This\n");
642 log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
643 log("pass is using the current design as mapping library.\n");
644 log("\n");
645 }
646 virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
647 {
648 log_header("Executing FLATTEN pass (flatten design).\n");
649 log_push();
650
651 extra_args(args, 1, design);
652
653 TechmapWorker worker;
654
655 std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
656 for (auto &it : design->modules)
657 celltypeMap[it.first].insert(it.first);
658
659 RTLIL::Module *top_mod = NULL;
660 if (design->full_selection())
661 for (auto &mod_it : design->modules)
662 if (mod_it.second->get_bool_attribute("\\top"))
663 top_mod = mod_it.second;
664
665 bool did_something = true;
666 std::set<RTLIL::Cell*> handled_cells;
667 while (did_something) {
668 did_something = false;
669 if (top_mod != NULL) {
670 if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
671 did_something = true;
672 } else {
673 for (auto &mod_it : design->modules)
674 if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
675 did_something = true;
676 }
677 }
678
679 log("No more expansions possible.\n");
680
681 if (top_mod != NULL) {
682 std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
683 for (auto &mod_it : design->modules)
684 if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) {
685 new_modules[mod_it.first] = mod_it.second;
686 } else {
687 log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
688 delete mod_it.second;
689 }
690 design->modules.swap(new_modules);
691 }
692
693 log_pop();
694 }
695 } FlattenPass;
696