2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
35 extern void maccmap(RTLIL::Module
*module
, RTLIL::Cell
*cell
, bool unmap
= false);
40 PRIVATE_NAMESPACE_BEGIN
42 void apply_prefix(IdString prefix
, IdString
&id
)
45 id
= stringf("%s.%s", prefix
.c_str(), id
.c_str()+1);
47 id
= stringf("$techmap%s.%s", prefix
.c_str(), id
.c_str());
50 void apply_prefix(IdString prefix
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
)
52 vector
<SigChunk
> chunks
= sig
;
53 for (auto &chunk
: chunks
)
54 if (chunk
.wire
!= NULL
) {
55 IdString wire_name
= chunk
.wire
->name
;
56 apply_prefix(prefix
, wire_name
);
57 log_assert(module
->wires_
.count(wire_name
) > 0);
58 chunk
.wire
= module
->wires_
[wire_name
];
65 std::map
<RTLIL::IdString
, void(*)(RTLIL::Module
*, RTLIL::Cell
*)> simplemap_mappers
;
66 std::map
<std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>>, RTLIL::Module
*> techmap_cache
;
67 std::map
<RTLIL::Module
*, bool> techmap_do_cache
;
68 std::set
<RTLIL::Module
*, RTLIL::IdString::compare_ptr_by_name
<RTLIL::Module
>> module_queue
;
69 dict
<Module
*, SigMap
> sigmaps
;
71 pool
<IdString
> flatten_do_list
;
72 pool
<IdString
> flatten_done_list
;
73 pool
<Cell
*> flatten_keep_list
;
75 pool
<string
> log_msg_cache
;
77 struct TechmapWireData
{
82 typedef std::map
<std::string
, std::vector
<TechmapWireData
>> TechmapWires
;
96 recursive_mode
= false;
97 autoproc_mode
= false;
101 std::string
constmap_tpl_name(SigMap
&sigmap
, RTLIL::Module
*tpl
, RTLIL::Cell
*cell
, bool verbose
)
103 std::string constmap_info
;
104 std::map
<RTLIL::SigBit
, std::pair
<RTLIL::IdString
, int>> connbits_map
;
106 for (auto conn
: cell
->connections())
107 for (int i
= 0; i
< GetSize(conn
.second
); i
++) {
108 RTLIL::SigBit bit
= sigmap(conn
.second
[i
]);
109 if (bit
.wire
== nullptr) {
111 log(" Constant input on bit %d of port %s: %s\n", i
, log_id(conn
.first
), log_signal(bit
));
112 constmap_info
+= stringf("|%s %d %d", log_id(conn
.first
), i
, bit
.data
);
113 } else if (connbits_map
.count(bit
)) {
115 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i
, log_id(conn
.first
),
116 connbits_map
.at(bit
).second
, log_id(connbits_map
.at(bit
).first
));
117 constmap_info
+= stringf("|%s %d %s %d", log_id(conn
.first
), i
,
118 log_id(connbits_map
.at(bit
).first
), connbits_map
.at(bit
).second
);
120 connbits_map
[bit
] = std::pair
<RTLIL::IdString
, int>(conn
.first
, i
);
121 constmap_info
+= stringf("|%s %d", log_id(conn
.first
), i
);
125 return stringf("$paramod$constmap:%s%s", sha1(constmap_info
).c_str(), tpl
->name
.c_str());
128 TechmapWires
techmap_find_special_wires(RTLIL::Module
*module
)
135 for (auto &it
: module
->wires_
) {
136 const char *p
= it
.first
.c_str();
140 const char *q
= strrchr(p
+1, '.');
143 if (!strncmp(p
, "_TECHMAP_", 9)) {
144 TechmapWireData record
;
145 record
.wire
= it
.second
;
146 record
.value
= it
.second
;
147 result
[p
].push_back(record
);
148 it
.second
->attributes
[ID::keep
] = RTLIL::Const(1);
149 it
.second
->attributes
[ID(_techmap_special_
)] = RTLIL::Const(1);
153 if (!result
.empty()) {
154 SigMap
sigmap(module
);
155 for (auto &it1
: result
)
156 for (auto &it2
: it1
.second
)
157 sigmap
.apply(it2
.value
);
163 void techmap_module_worker(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Cell
*cell
, RTLIL::Module
*tpl
)
165 if (tpl
->processes
.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it
: tpl
->processes
)
168 log(" %s",RTLIL::id2cstr(it
.first
));
171 Pass::call_on_module(tpl
->design
, tpl
, "proc");
172 log_assert(GetSize(tpl
->processes
) == 0);
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
177 std::string orig_cell_name
;
178 pool
<string
> extra_src_attrs
= cell
->get_strpool_attribute(ID(src
));
181 for (auto &it
: tpl
->cells_
)
182 if (it
.first
== ID(_TECHMAP_REPLACE_
)) {
183 orig_cell_name
= cell
->name
.str();
184 module
->rename(cell
, stringf("$techmap%d", autoidx
++) + cell
->name
.str());
189 dict
<IdString
, IdString
> memory_renames
;
191 for (auto &it
: tpl
->memories
) {
192 IdString m_name
= it
.first
;
193 apply_prefix(cell
->name
, m_name
);
194 RTLIL::Memory
*m
= new RTLIL::Memory
;
196 m
->width
= it
.second
->width
;
197 m
->start_offset
= it
.second
->start_offset
;
198 m
->size
= it
.second
->size
;
199 m
->attributes
= it
.second
->attributes
;
200 if (m
->attributes
.count(ID(src
)))
201 m
->add_strpool_attribute(ID(src
), extra_src_attrs
);
202 module
->memories
[m
->name
] = m
;
203 memory_renames
[it
.first
] = m
->name
;
204 design
->select(module
, m
);
207 std::map
<RTLIL::IdString
, RTLIL::IdString
> positional_ports
;
208 dict
<Wire
*, IdString
> temp_renamed_wires
;
210 for (auto &it
: tpl
->wires_
) {
211 if (it
.second
->port_id
> 0)
212 positional_ports
[stringf("$%d", it
.second
->port_id
)] = it
.first
;
213 IdString w_name
= it
.second
->name
;
214 apply_prefix(cell
->name
, w_name
);
215 RTLIL::Wire
*w
= module
->wire(w_name
);
217 if (!flatten_mode
|| !w
->get_bool_attribute(ID(hierconn
))) {
218 temp_renamed_wires
[w
] = w
->name
;
219 module
->rename(w
, NEW_ID
);
222 w
->attributes
.erase(ID(hierconn
));
223 if (GetSize(w
) < GetSize(it
.second
)) {
224 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module
), log_id(w
),
225 log_id(tpl
), log_id(it
.second
), log_id(module
), log_id(cell
));
226 w
->width
= GetSize(it
.second
);
231 w
= module
->addWire(w_name
, it
.second
);
232 w
->port_input
= false;
233 w
->port_output
= false;
235 if (it
.second
->get_bool_attribute(ID(_techmap_special_
)))
236 w
->attributes
.clear();
237 if (w
->attributes
.count(ID(src
)))
238 w
->add_strpool_attribute(ID(src
), extra_src_attrs
);
240 design
->select(module
, w
);
243 SigMap
tpl_sigmap(tpl
);
244 pool
<SigBit
> tpl_written_bits
;
246 for (auto &it1
: tpl
->cells_
)
247 for (auto &it2
: it1
.second
->connections_
)
248 if (it1
.second
->output(it2
.first
))
249 for (auto bit
: tpl_sigmap(it2
.second
))
250 tpl_written_bits
.insert(bit
);
251 for (auto &it1
: tpl
->connections_
)
252 for (auto bit
: tpl_sigmap(it1
.first
))
253 tpl_written_bits
.insert(bit
);
255 SigMap port_signal_map
;
256 SigSig port_signal_assign
;
258 for (auto &it
: cell
->connections())
260 RTLIL::IdString portname
= it
.first
;
261 if (positional_ports
.count(portname
) > 0)
262 portname
= positional_ports
.at(portname
);
263 if (tpl
->wires_
.count(portname
) == 0 || tpl
->wires_
.at(portname
)->port_id
== 0) {
264 if (portname
.begins_with("$"))
265 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname
.c_str(), cell
->name
.c_str(), tpl
->name
.c_str());
269 if (GetSize(it
.second
) == 0)
272 RTLIL::Wire
*w
= tpl
->wires_
.at(portname
);
273 RTLIL::SigSig c
, extra_connect
;
275 if (w
->port_output
&& !w
->port_input
) {
277 c
.second
= RTLIL::SigSpec(w
);
278 apply_prefix(cell
->name
, c
.second
, module
);
279 extra_connect
.first
= c
.second
;
280 extra_connect
.second
= c
.first
;
281 } else if (!w
->port_output
&& w
->port_input
) {
282 c
.first
= RTLIL::SigSpec(w
);
283 c
.second
= it
.second
;
284 apply_prefix(cell
->name
, c
.first
, module
);
285 extra_connect
.first
= c
.first
;
286 extra_connect
.second
= c
.second
;
288 SigSpec sig_tpl
= w
, sig_tpl_pf
= w
, sig_mod
= it
.second
;
289 apply_prefix(cell
->name
, sig_tpl_pf
, module
);
290 for (int i
= 0; i
< GetSize(sig_tpl
) && i
< GetSize(sig_mod
); i
++) {
291 if (tpl_written_bits
.count(tpl_sigmap(sig_tpl
[i
]))) {
292 c
.first
.append(sig_mod
[i
]);
293 c
.second
.append(sig_tpl_pf
[i
]);
295 c
.first
.append(sig_tpl_pf
[i
]);
296 c
.second
.append(sig_mod
[i
]);
299 extra_connect
.first
= sig_tpl_pf
;
300 extra_connect
.second
= sig_mod
;
303 if (c
.second
.size() > c
.first
.size())
304 c
.second
.remove(c
.first
.size(), c
.second
.size() - c
.first
.size());
306 if (c
.second
.size() < c
.first
.size())
307 c
.second
.append(RTLIL::SigSpec(RTLIL::State::S0
, c
.first
.size() - c
.second
.size()));
309 log_assert(c
.first
.size() == c
.second
.size());
313 // more conservative approach:
314 // connect internal and external wires
316 if (sigmaps
.count(module
) == 0)
317 sigmaps
[module
].set(module
);
319 if (sigmaps
.at(module
)(c
.first
).has_const())
320 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
321 log_id(module
), log_id(cell
), log_id(it
.first
), log_signal(c
.first
), log_signal(c
.second
));
327 // approach that yields nicer outputs:
328 // replace internal wires that are connected to external wires
330 if (w
->port_output
&& !w
->port_input
) {
331 port_signal_map
.add(c
.second
, c
.first
);
333 if (!w
->port_output
&& w
->port_input
) {
334 port_signal_map
.add(c
.first
, c
.second
);
337 extra_connect
= SigSig();
340 for (auto &attr
: w
->attributes
) {
341 if (attr
.first
== ID(src
))
343 module
->connect(extra_connect
);
349 for (auto &it
: tpl
->cells_
)
351 IdString c_name
= it
.second
->name
.str();
352 bool techmap_replace_cell
= (!flatten_mode
) && (c_name
== ID(_TECHMAP_REPLACE_
));
354 if (techmap_replace_cell
)
355 c_name
= orig_cell_name
;
357 apply_prefix(cell
->name
, c_name
);
359 RTLIL::Cell
*c
= module
->addCell(c_name
, it
.second
);
360 design
->select(module
, c
);
362 if (!flatten_mode
&& c
->type
.begins_with("\\$"))
363 c
->type
= c
->type
.substr(1);
365 for (auto &it2
: c
->connections_
) {
366 apply_prefix(cell
->name
, it2
.second
, module
);
367 port_signal_map
.apply(it2
.second
);
370 if (c
->type
.in(ID($memrd
), ID($memwr
), ID($meminit
))) {
371 IdString memid
= c
->getParam(ID(MEMID
)).decode_string();
372 log_assert(memory_renames
.count(memid
) != 0);
373 c
->setParam(ID(MEMID
), Const(memory_renames
[memid
].str()));
376 if (c
->type
== ID($mem
)) {
377 IdString memid
= c
->getParam(ID(MEMID
)).decode_string();
378 apply_prefix(cell
->name
, memid
);
379 c
->setParam(ID(MEMID
), Const(memid
.c_str()));
382 if (c
->attributes
.count(ID(src
)))
383 c
->add_strpool_attribute(ID(src
), extra_src_attrs
);
385 if (techmap_replace_cell
)
386 for (auto attr
: cell
->attributes
)
387 if (!c
->attributes
.count(attr
.first
))
388 c
->attributes
[attr
.first
] = attr
.second
;
391 for (auto &it
: tpl
->connections()) {
392 RTLIL::SigSig c
= it
;
393 apply_prefix(cell
->name
.str(), c
.first
, module
);
394 apply_prefix(cell
->name
.str(), c
.second
, module
);
395 port_signal_map
.apply(c
.first
);
396 port_signal_map
.apply(c
.second
);
400 module
->remove(cell
);
402 for (auto &it
: temp_renamed_wires
)
405 IdString name
= it
.second
;
406 IdString altname
= module
->uniquify(name
);
407 Wire
*other_w
= module
->wire(name
);
408 module
->rename(other_w
, altname
);
409 module
->rename(w
, name
);
413 bool techmap_module(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Design
*map
, std::set
<RTLIL::Cell
*> &handled_cells
,
414 const std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> &celltypeMap
, bool in_recursion
)
416 std::string mapmsg_prefix
= in_recursion
? "Recursively mapping" : "Mapping";
418 if (!design
->selected(module
) || module
->get_blackbox_attribute(ignore_wb
))
421 bool log_continue
= false;
422 bool did_something
= false;
423 LogMakeDebugHdl mkdebug
;
425 SigMap
sigmap(module
);
427 dict
<SigBit
, State
> init_bits
;
428 pool
<SigBit
> remove_init_bits
;
430 for (auto wire
: module
->wires()) {
431 if (wire
->attributes
.count("\\init")) {
432 Const value
= wire
->attributes
.at("\\init");
433 for (int i
= 0; i
< min(GetSize(value
), GetSize(wire
)); i
++)
434 if (value
[i
] != State::Sx
)
435 init_bits
[sigmap(SigBit(wire
, i
))] = value
[i
];
439 TopoSort
<RTLIL::Cell
*, RTLIL::IdString::compare_ptr_by_name
<RTLIL::Cell
>> cells
;
440 std::map
<RTLIL::Cell
*, std::set
<RTLIL::SigBit
>> cell_to_inbit
;
441 std::map
<RTLIL::SigBit
, std::set
<RTLIL::Cell
*>> outbit_to_cell
;
443 for (auto cell
: module
->cells())
445 if (!design
->selected(module
, cell
) || handled_cells
.count(cell
) > 0)
448 std::string cell_type
= cell
->type
.str();
449 if (in_recursion
&& cell
->type
.begins_with("\\$"))
450 cell_type
= cell_type
.substr(1);
452 if (celltypeMap
.count(cell_type
) == 0) {
453 if (assert_mode
&& cell_type
.back() != '_')
454 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type
));
459 bool keepit
= cell
->get_bool_attribute(ID(keep_hierarchy
));
460 for (auto &tpl_name
: celltypeMap
.at(cell_type
))
461 if (map
->modules_
[tpl_name
]->get_bool_attribute(ID(keep_hierarchy
)))
464 if (!flatten_keep_list
[cell
]) {
465 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module
), log_id(cell
));
466 flatten_keep_list
.insert(cell
);
468 if (!flatten_done_list
[cell
->type
])
469 flatten_do_list
.insert(cell
->type
);
474 for (auto &conn
: cell
->connections())
476 RTLIL::SigSpec sig
= sigmap(conn
.second
);
479 if (GetSize(sig
) == 0)
482 for (auto &tpl_name
: celltypeMap
.at(cell_type
)) {
483 RTLIL::Module
*tpl
= map
->modules_
[tpl_name
];
484 RTLIL::Wire
*port
= tpl
->wire(conn
.first
);
485 if (port
&& port
->port_input
)
486 cell_to_inbit
[cell
].insert(sig
.begin(), sig
.end());
487 if (port
&& port
->port_output
)
488 for (auto &bit
: sig
)
489 outbit_to_cell
[bit
].insert(cell
);
496 for (auto &it_right
: cell_to_inbit
)
497 for (auto &it_sigbit
: it_right
.second
)
498 for (auto &it_left
: outbit_to_cell
[it_sigbit
])
499 cells
.edge(it_left
, it_right
.first
);
503 for (auto cell
: cells
.sorted
)
505 log_assert(handled_cells
.count(cell
) == 0);
506 log_assert(cell
== module
->cell(cell
->name
));
507 bool mapped_cell
= false;
509 std::string cell_type
= cell
->type
.str();
511 if (in_recursion
&& cell
->type
.begins_with("\\$"))
512 cell_type
= cell_type
.substr(1);
514 for (auto &tpl_name
: celltypeMap
.at(cell_type
))
516 RTLIL::IdString derived_name
= tpl_name
;
517 RTLIL::Module
*tpl
= map
->modules_
[tpl_name
];
518 std::map
<RTLIL::IdString
, RTLIL::Const
> parameters(cell
->parameters
.begin(), cell
->parameters
.end());
520 if (tpl
->get_blackbox_attribute(ignore_wb
))
525 std::string extmapper_name
;
527 if (tpl
->get_bool_attribute(ID(techmap_simplemap
)))
528 extmapper_name
= "simplemap";
530 if (tpl
->get_bool_attribute(ID(techmap_maccmap
)))
531 extmapper_name
= "maccmap";
533 if (tpl
->attributes
.count(ID(techmap_wrap
)))
534 extmapper_name
= "wrap";
536 if (!extmapper_name
.empty())
538 cell
->type
= cell_type
;
540 if ((extern_mode
&& !in_recursion
) || extmapper_name
== "wrap")
542 std::string m_name
= stringf("$extern:%s:%s", extmapper_name
.c_str(), log_id(cell
->type
));
544 for (auto &c
: cell
->parameters
)
545 m_name
+= stringf(":%s=%s", log_id(c
.first
), log_signal(c
.second
));
547 if (extmapper_name
== "wrap")
548 m_name
+= ":" + sha1(tpl
->attributes
.at(ID(techmap_wrap
)).decode_string());
550 RTLIL::Design
*extmapper_design
= extern_mode
&& !in_recursion
? design
: tpl
->design
;
551 RTLIL::Module
*extmapper_module
= extmapper_design
->module(m_name
);
553 if (extmapper_module
== nullptr)
555 extmapper_module
= extmapper_design
->addModule(m_name
);
556 RTLIL::Cell
*extmapper_cell
= extmapper_module
->addCell(cell
->type
, cell
);
558 extmapper_cell
->set_src_attribute(cell
->get_src_attribute());
560 int port_counter
= 1;
561 for (auto &c
: extmapper_cell
->connections_
) {
562 RTLIL::Wire
*w
= extmapper_module
->addWire(c
.first
, GetSize(c
.second
));
563 if (w
->name
.in(ID::Y
, ID(Q
)))
564 w
->port_output
= true;
566 w
->port_input
= true;
567 w
->port_id
= port_counter
++;
571 extmapper_module
->fixup_ports();
572 extmapper_module
->check();
574 if (extmapper_name
== "simplemap") {
575 log("Creating %s with simplemap.\n", log_id(extmapper_module
));
576 if (simplemap_mappers
.count(extmapper_cell
->type
) == 0)
577 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell
->type
));
578 simplemap_mappers
.at(extmapper_cell
->type
)(extmapper_module
, extmapper_cell
);
579 extmapper_module
->remove(extmapper_cell
);
582 if (extmapper_name
== "maccmap") {
583 log("Creating %s with maccmap.\n", log_id(extmapper_module
));
584 if (extmapper_cell
->type
!= ID($macc
))
585 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell
->type
));
586 maccmap(extmapper_module
, extmapper_cell
);
587 extmapper_module
->remove(extmapper_cell
);
590 if (extmapper_name
== "wrap") {
591 std::string cmd_string
= tpl
->attributes
.at(ID(techmap_wrap
)).decode_string();
592 log("Running \"%s\" on wrapper %s.\n", cmd_string
.c_str(), log_id(extmapper_module
));
594 Pass::call_on_module(extmapper_design
, extmapper_module
, cmd_string
);
599 cell
->type
= extmapper_module
->name
;
600 cell
->parameters
.clear();
602 if (!extern_mode
|| in_recursion
) {
603 tpl
= extmapper_module
;
604 goto use_wrapper_tpl
;
607 auto msg
= stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module
), log_id(cell
->type
));
608 if (!log_msg_cache
.count(msg
)) {
609 log_msg_cache
.insert(msg
);
610 log("%s\n", msg
.c_str());
612 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), log_id(extmapper_module
));
616 auto msg
= stringf("Using extmapper %s for cells of type %s.", extmapper_name
.c_str(), log_id(cell
->type
));
617 if (!log_msg_cache
.count(msg
)) {
618 log_msg_cache
.insert(msg
);
619 log("%s\n", msg
.c_str());
621 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), extmapper_name
.c_str());
623 if (extmapper_name
== "simplemap") {
624 if (simplemap_mappers
.count(cell
->type
) == 0)
625 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell
->type
));
626 simplemap_mappers
.at(cell
->type
)(module
, cell
);
629 if (extmapper_name
== "maccmap") {
630 if (cell
->type
!= ID($macc
))
631 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell
->type
));
632 maccmap(module
, cell
);
635 module
->remove(cell
);
639 did_something
= true;
644 for (auto conn
: cell
->connections()) {
645 if (conn
.first
.begins_with("$"))
647 if (tpl
->wires_
.count(conn
.first
) > 0 && tpl
->wires_
.at(conn
.first
)->port_id
> 0)
649 if (!conn
.second
.is_fully_const() || parameters
.count(conn
.first
) > 0 || tpl
->avail_parameters
.count(conn
.first
) == 0)
651 parameters
[conn
.first
] = conn
.second
.as_const();
659 if (tpl
->avail_parameters
.count(ID(_TECHMAP_CELLTYPE_
)) != 0)
660 parameters
[ID(_TECHMAP_CELLTYPE_
)] = RTLIL::unescape_id(cell
->type
);
662 for (auto conn
: cell
->connections()) {
663 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
664 std::vector
<RTLIL::SigBit
> v
= sigmap(conn
.second
).to_sigbit_vector();
666 bit
= RTLIL::SigBit(bit
.wire
== NULL
? RTLIL::State::S1
: RTLIL::State::S0
);
667 parameters
[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn
.first
))] = RTLIL::SigSpec(v
).as_const();
669 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
670 std::vector
<RTLIL::SigBit
> v
= sigmap(conn
.second
).to_sigbit_vector();
672 if (bit
.wire
!= NULL
)
673 bit
= RTLIL::SigBit(RTLIL::State::Sx
);
674 parameters
[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn
.first
))] = RTLIL::SigSpec(v
).as_const();
676 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
677 auto sig
= sigmap(conn
.second
);
678 RTLIL::Const
value(State::Sx
, sig
.size());
679 for (int i
= 0; i
< sig
.size(); i
++) {
680 auto it
= init_bits
.find(sig
[i
]);
681 if (it
!= init_bits
.end()) {
682 value
[i
] = it
->second
;
685 parameters
[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn
.first
))] = value
;
689 int unique_bit_id_counter
= 0;
690 std::map
<RTLIL::SigBit
, int> unique_bit_id
;
691 unique_bit_id
[RTLIL::State::S0
] = unique_bit_id_counter
++;
692 unique_bit_id
[RTLIL::State::S1
] = unique_bit_id_counter
++;
693 unique_bit_id
[RTLIL::State::Sx
] = unique_bit_id_counter
++;
694 unique_bit_id
[RTLIL::State::Sz
] = unique_bit_id_counter
++;
696 for (auto conn
: cell
->connections())
697 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
698 for (auto &bit
: sigmap(conn
.second
).to_sigbit_vector())
699 if (unique_bit_id
.count(bit
) == 0)
700 unique_bit_id
[bit
] = unique_bit_id_counter
++;
703 // Find highest bit set
705 for (int i
= 0; i
< 32; i
++)
706 if (((unique_bit_id_counter
-1) & (1 << i
)) != 0)
708 // Increment index by one to get number of bits
710 if (tpl
->avail_parameters
.count(ID(_TECHMAP_BITS_CONNMAP_
)))
711 parameters
[ID(_TECHMAP_BITS_CONNMAP_
)] = bits
;
713 for (auto conn
: cell
->connections())
714 if (tpl
->avail_parameters
.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))) != 0) {
716 for (auto &bit
: sigmap(conn
.second
).to_sigbit_vector()) {
717 RTLIL::Const
chunk(unique_bit_id
.at(bit
), bits
);
718 value
.bits
.insert(value
.bits
.end(), chunk
.bits
.begin(), chunk
.bits
.end());
720 parameters
[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn
.first
))] = value
;
726 // do not register techmap_wrap modules with techmap_cache
728 std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>> key(tpl_name
, parameters
);
729 if (techmap_cache
.count(key
) > 0) {
730 tpl
= techmap_cache
[key
];
732 if (parameters
.size() != 0) {
734 derived_name
= tpl
->derive(map
, dict
<RTLIL::IdString
, RTLIL::Const
>(parameters
.begin(), parameters
.end()));
735 tpl
= map
->module(derived_name
);
738 techmap_cache
[key
] = tpl
;
743 techmap_do_cache
[tpl
] = true;
745 RTLIL::Module
*constmapped_tpl
= map
->module(constmap_tpl_name(sigmap
, tpl
, cell
, false));
746 if (constmapped_tpl
!= nullptr)
747 tpl
= constmapped_tpl
;
750 if (techmap_do_cache
.count(tpl
) == 0)
752 bool keep_running
= true;
753 techmap_do_cache
[tpl
] = true;
755 std::set
<std::string
> techmap_wire_names
;
759 TechmapWires twd
= techmap_find_special_wires(tpl
);
760 keep_running
= false;
763 techmap_wire_names
.insert(it
.first
);
765 for (auto &it
: twd
["_TECHMAP_FAIL_"]) {
766 RTLIL::SigSpec value
= it
.value
;
767 if (value
.is_fully_const() && value
.as_bool()) {
768 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
769 derived_name
.c_str(), RTLIL::id2cstr(it
.wire
->name
), log_signal(value
));
770 techmap_do_cache
[tpl
] = false;
774 if (!techmap_do_cache
[tpl
])
779 if (it
.first
.compare(0, 12, "_TECHMAP_DO_") != 0 || it
.second
.empty())
782 auto &data
= it
.second
.front();
784 if (!data
.value
.is_fully_const())
785 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data
.wire
->name
), log_signal(data
.value
));
787 techmap_wire_names
.erase(it
.first
);
789 const char *p
= data
.wire
->name
.c_str();
790 const char *q
= strrchr(p
+1, '.');
793 std::string cmd_string
= data
.value
.as_const().decode_string();
795 restart_eval_cmd_string
:
796 if (cmd_string
.rfind("CONSTMAP; ", 0) == 0)
798 cmd_string
= cmd_string
.substr(strlen("CONSTMAP; "));
800 log("Analyzing pattern of constant bits for this cell:\n");
801 RTLIL::IdString new_tpl_name
= constmap_tpl_name(sigmap
, tpl
, cell
, true);
802 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name
));
803 log_assert(map
->module(new_tpl_name
) == nullptr);
805 RTLIL::Module
*new_tpl
= map
->addModule(new_tpl_name
);
806 tpl
->cloneInto(new_tpl
);
808 techmap_do_cache
.erase(tpl
);
809 techmap_do_cache
[new_tpl
] = true;
812 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> port_new2old_map
;
813 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> port_connmap
;
814 std::map
<RTLIL::SigBit
, RTLIL::SigBit
> cellbits_to_tplbits
;
816 for (auto wire
: tpl
->wires().to_vector())
818 if (!wire
->port_input
|| wire
->port_output
)
821 RTLIL::IdString port_name
= wire
->name
;
822 tpl
->rename(wire
, NEW_ID
);
824 RTLIL::Wire
*new_wire
= tpl
->addWire(port_name
, wire
);
825 wire
->port_input
= false;
828 for (int i
= 0; i
< wire
->width
; i
++) {
829 port_new2old_map
[RTLIL::SigBit(new_wire
, i
)] = RTLIL::SigBit(wire
, i
);
830 port_connmap
[RTLIL::SigBit(wire
, i
)] = RTLIL::SigBit(new_wire
, i
);
834 for (auto conn
: cell
->connections())
835 for (int i
= 0; i
< GetSize(conn
.second
); i
++)
837 RTLIL::SigBit bit
= sigmap(conn
.second
[i
]);
838 RTLIL::SigBit
tplbit(tpl
->wire(conn
.first
), i
);
840 if (bit
.wire
== nullptr)
842 RTLIL::SigBit oldbit
= port_new2old_map
.at(tplbit
);
843 port_connmap
.at(oldbit
) = bit
;
845 else if (cellbits_to_tplbits
.count(bit
))
847 RTLIL::SigBit oldbit
= port_new2old_map
.at(tplbit
);
848 port_connmap
.at(oldbit
) = cellbits_to_tplbits
[bit
];
851 cellbits_to_tplbits
[bit
] = tplbit
;
854 RTLIL::SigSig port_conn
;
855 for (auto &it
: port_connmap
) {
856 port_conn
.first
.append_bit(it
.first
);
857 port_conn
.second
.append_bit(it
.second
);
859 tpl
->connect(port_conn
);
862 goto restart_eval_cmd_string
;
865 if (cmd_string
.rfind("RECURSION; ", 0) == 0)
867 cmd_string
= cmd_string
.substr(strlen("RECURSION; "));
868 while (techmap_module(map
, tpl
, map
, handled_cells
, celltypeMap
, true)) { }
869 goto restart_eval_cmd_string
;
872 Pass::call_on_module(map
, tpl
, cmd_string
);
874 log_assert(!strncmp(q
, "_TECHMAP_DO_", 12));
875 std::string new_name
= data
.wire
->name
.substr(0, q
-p
) + "_TECHMAP_DONE_" + data
.wire
->name
.substr(q
-p
+12);
876 while (tpl
->wires_
.count(new_name
))
878 tpl
->rename(data
.wire
->name
, new_name
);
885 TechmapWires twd
= techmap_find_special_wires(tpl
);
886 for (auto &it
: twd
) {
887 if (it
.first
!= "_TECHMAP_FAIL_" && (it
.first
.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it
.first
[it
.first
.size()-1] != '_') && it
.first
.substr(0, 12) != "_TECHMAP_DO_" && it
.first
.substr(0, 14) != "_TECHMAP_DONE_")
888 log_error("Techmap yielded unknown config wire %s.\n", it
.first
.c_str());
889 if (techmap_do_cache
[tpl
])
890 for (auto &it2
: it
.second
)
891 if (!it2
.value
.is_fully_const())
892 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2
.wire
->name
), log_signal(it2
.value
));
893 if (it
.first
.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache
[tpl
]) {
894 for (auto &it2
: it
.second
) {
895 auto val
= it2
.value
.as_const();
896 auto wirename
= RTLIL::escape_id(it
.first
.substr(20, it
.first
.size() - 20 - 1));
897 auto it
= cell
->connections().find(wirename
);
898 if (it
!= cell
->connections().end()) {
899 auto sig
= sigmap(it
->second
);
900 for (int i
= 0; i
< sig
.size(); i
++)
901 if (val
[i
] == State::S1
)
902 remove_init_bits
.insert(sig
[i
]);
906 techmap_wire_names
.erase(it
.first
);
909 for (auto &it
: techmap_wire_names
)
910 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it
));
912 if (recursive_mode
) {
914 log_header(design
, "Continuing TECHMAP pass.\n");
915 log_continue
= false;
918 while (techmap_module(map
, tpl
, map
, handled_cells
, celltypeMap
, true)) { }
922 if (techmap_do_cache
.at(tpl
) == false)
926 log_header(design
, "Continuing TECHMAP pass.\n");
927 log_continue
= false;
931 if (extern_mode
&& !in_recursion
)
933 std::string m_name
= stringf("$extern:%s", log_id(tpl
));
935 if (!design
->module(m_name
))
937 RTLIL::Module
*m
= design
->addModule(m_name
);
940 for (auto cell
: m
->cells()) {
941 if (cell
->type
.begins_with("\\$"))
942 cell
->type
= cell
->type
.substr(1);
945 module_queue
.insert(m
);
948 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(m_name
));
950 cell
->parameters
.clear();
954 auto msg
= stringf("Using template %s for cells of type %s.", log_id(tpl
), log_id(cell
->type
));
955 if (!log_msg_cache
.count(msg
)) {
956 log_msg_cache
.insert(msg
);
957 log("%s\n", msg
.c_str());
959 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix
.c_str(), log_id(module
), log_id(cell
), log_id(cell
->type
), log_id(tpl
));
960 techmap_module_worker(design
, module
, cell
, tpl
);
963 did_something
= true;
968 if (assert_mode
&& !mapped_cell
)
969 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module
), log_id(cell
), log_id(cell
->type
));
971 handled_cells
.insert(cell
);
974 if (!remove_init_bits
.empty()) {
975 for (auto wire
: module
->wires())
976 if (wire
->attributes
.count("\\init")) {
977 Const
&value
= wire
->attributes
.at("\\init");
978 bool do_cleanup
= true;
979 for (int i
= 0; i
< min(GetSize(value
), GetSize(wire
)); i
++) {
980 SigBit bit
= sigmap(SigBit(wire
, i
));
981 if (remove_init_bits
.count(bit
))
982 value
[i
] = State::Sx
;
983 else if (value
[i
] != State::Sx
)
987 log("Removing init attribute from wire %s.%s.\n", log_id(module
), log_id(wire
));
988 wire
->attributes
.erase("\\init");
994 log_header(design
, "Continuing TECHMAP pass.\n");
995 log_continue
= false;
999 return did_something
;
1003 struct TechmapPass
: public Pass
{
1004 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1005 void help() YS_OVERRIDE
1007 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1009 log(" techmap [-map filename] [selection]\n");
1011 log("This pass implements a very simple technology mapper that replaces cells in\n");
1012 log("the design with implementations given in form of a Verilog or ilang source\n");
1015 log(" -map filename\n");
1016 log(" the library of cell implementations to be used.\n");
1017 log(" without this parameter a builtin library is used that\n");
1018 log(" transforms the internal RTL cells to the internal gate\n");
1021 log(" -map %%<design-name>\n");
1022 log(" like -map above, but with an in-memory design instead of a file.\n");
1025 log(" load the cell implementations as separate modules into the design\n");
1026 log(" instead of inlining them.\n");
1028 log(" -max_iter <number>\n");
1029 log(" only run the specified number of iterations on each module.\n");
1030 log(" default: unlimited\n");
1032 log(" -recursive\n");
1033 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1034 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1035 log(" but may differ in performance.\n");
1037 log(" -autoproc\n");
1038 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1041 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1044 log(" this option will cause techmap to exit with an error if it can't map\n");
1045 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1046 log(" as final cell types by this mode.\n");
1048 log(" -D <define>, -I <incdir>\n");
1049 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1050 log(" map file. Note that the Verilog frontend is also called with the\n");
1051 log(" '-nooverwrite' option set.\n");
1053 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1054 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1055 log("the module name will be used to match the cell.\n");
1057 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1058 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1060 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1061 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1063 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1064 log("will create a wrapper for the cell and then run the command string that the\n");
1065 log("attribute is set to on the wrapper module.\n");
1067 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1068 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1069 log("the mapping module to the techmap command. At the moment the following special\n");
1070 log("wires are supported:\n");
1072 log(" _TECHMAP_FAIL_\n");
1073 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1074 log(" use this module and instead try the next module with a matching\n");
1075 log(" 'techmap_celltype' attribute.\n");
1077 log(" When such a wire exists but does not have a constant value after all\n");
1078 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1080 log(" _TECHMAP_DO_*\n");
1081 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1082 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1083 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1084 log(" that are written using always-statements.\n");
1086 log(" When such a wire has a non-constant value at the time it is to be\n");
1087 log(" evaluated, an error is produced. That means it is possible for such a\n");
1088 log(" wire to start out as non-constant and evaluate to a constant value\n");
1089 log(" during processing of other _TECHMAP_DO_* commands.\n");
1091 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1092 log(" in this case techmap will create a copy for each distinct configuration\n");
1093 log(" of constant inputs and shorted inputs at this point and import the\n");
1094 log(" constant and connected bits into the map module. All further commands\n");
1095 log(" are executed in this copy. This is a very convenient way of creating\n");
1096 log(" optimized specializations of techmap modules without using the special\n");
1097 log(" parameters described below.\n");
1099 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1100 log(" then techmap will recursively replace the cells in the module with their\n");
1101 log(" implementation. This is not affected by the -max_iter option.\n");
1103 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1105 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1106 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1107 log(" connected to this port will be consumed. This wire must have the same\n");
1108 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1109 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1110 log(" bits of an init attribute are left as x, it will be removed.\n");
1112 log("In addition to this special wires, techmap also supports special parameters in\n");
1113 log("modules in the map file:\n");
1115 log(" _TECHMAP_CELLTYPE_\n");
1116 log(" When a parameter with this name exists, it will be set to the type name\n");
1117 log(" of the cell that matches the module.\n");
1119 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1120 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1121 log(" When this pair of parameters is available in a module for a port, then\n");
1122 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1123 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1125 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1126 log(" When a parameter with this name exists, it will be set to the initial\n");
1127 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1128 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1129 log(" missing bits. To remove the init attribute bits used, use the\n");
1130 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1132 log(" _TECHMAP_BITS_CONNMAP_\n");
1133 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1134 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1135 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1136 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1137 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1138 log(" This can be used to detect shorted inputs.\n");
1140 log("When a module in the map file has a parameter where the according cell in the\n");
1141 log("design has a port, the module from the map file is only used if the port in\n");
1142 log("the design is connected to a constant value. The parameter is then set to the\n");
1143 log("constant value.\n");
1145 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1146 log("and attributes of the cell that is being replaced.\n");
1148 log("See 'help extract' for a pass that does the opposite thing.\n");
1150 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1151 log("essentially techmap but using the design itself as map library).\n");
1154 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1156 log_header(design
, "Executing TECHMAP pass (map to technology primitives).\n");
1159 TechmapWorker worker
;
1160 simplemap_get_mappers(worker
.simplemap_mappers
);
1162 std::vector
<std::string
> map_files
;
1163 std::string verilog_frontend
= "verilog -nooverwrite -noblackbox";
1167 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
1168 if (args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
1169 map_files
.push_back(args
[++argidx
]);
1172 if (args
[argidx
] == "-max_iter" && argidx
+1 < args
.size()) {
1173 max_iter
= atoi(args
[++argidx
].c_str());
1176 if (args
[argidx
] == "-D" && argidx
+1 < args
.size()) {
1177 verilog_frontend
+= " -D " + args
[++argidx
];
1180 if (args
[argidx
] == "-I" && argidx
+1 < args
.size()) {
1181 verilog_frontend
+= " -I " + args
[++argidx
];
1184 if (args
[argidx
] == "-assert") {
1185 worker
.assert_mode
= true;
1188 if (args
[argidx
] == "-extern") {
1189 worker
.extern_mode
= true;
1192 if (args
[argidx
] == "-recursive") {
1193 worker
.recursive_mode
= true;
1196 if (args
[argidx
] == "-autoproc") {
1197 worker
.autoproc_mode
= true;
1200 if (args
[argidx
] == "-wb") {
1201 worker
.ignore_wb
= true;
1206 extra_args(args
, argidx
, design
);
1208 RTLIL::Design
*map
= new RTLIL::Design
;
1209 if (map_files
.empty()) {
1210 std::istringstream
f(stdcells_code
);
1211 Frontend::frontend_call(map
, &f
, "<techmap.v>", verilog_frontend
);
1213 for (auto &fn
: map_files
)
1214 if (fn
.compare(0, 1, "%") == 0) {
1215 if (!saved_designs
.count(fn
.substr(1))) {
1217 log_cmd_error("Can't saved design `%s'.\n", fn
.c_str()+1);
1219 for (auto mod
: saved_designs
.at(fn
.substr(1))->modules())
1220 if (!map
->has(mod
->name
))
1221 map
->add(mod
->clone());
1224 rewrite_filename(fn
);
1226 yosys_input_files
.insert(fn
);
1228 log_cmd_error("Can't open map file `%s'\n", fn
.c_str());
1229 Frontend::frontend_call(map
, &f
, fn
, (fn
.size() > 3 && fn
.compare(fn
.size()-3, std::string::npos
, ".il") == 0 ? "ilang" : verilog_frontend
));
1233 log_header(design
, "Continuing TECHMAP pass.\n");
1235 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> celltypeMap
;
1236 for (auto &it
: map
->modules_
) {
1237 if (it
.second
->attributes
.count(ID(techmap_celltype
)) && !it
.second
->attributes
.at(ID(techmap_celltype
)).bits
.empty()) {
1238 char *p
= strdup(it
.second
->attributes
.at(ID(techmap_celltype
)).decode_string().c_str());
1239 for (char *q
= strtok(p
, " \t\r\n"); q
; q
= strtok(NULL
, " \t\r\n"))
1240 celltypeMap
[RTLIL::escape_id(q
)].insert(it
.first
);
1243 string module_name
= it
.first
.str();
1244 if (it
.first
.begins_with("\\$"))
1245 module_name
= module_name
.substr(1);
1246 celltypeMap
[module_name
].insert(it
.first
);
1250 for (auto module
: design
->modules())
1251 worker
.module_queue
.insert(module
);
1253 while (!worker
.module_queue
.empty())
1255 RTLIL::Module
*module
= *worker
.module_queue
.begin();
1256 worker
.module_queue
.erase(module
);
1258 int module_max_iter
= max_iter
;
1259 bool did_something
= true;
1260 std::set
<RTLIL::Cell
*> handled_cells
;
1261 while (did_something
) {
1262 did_something
= false;
1263 if (worker
.techmap_module(design
, module
, map
, handled_cells
, celltypeMap
, false))
1264 did_something
= true;
1267 if (module_max_iter
> 0 && --module_max_iter
== 0)
1272 log("No more expansions possible.\n");
1279 struct FlattenPass
: public Pass
{
1280 FlattenPass() : Pass("flatten", "flatten design") { }
1281 void help() YS_OVERRIDE
1283 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1285 log(" flatten [options] [selection]\n");
1287 log("This pass flattens the design by replacing cells by their implementation. This\n");
1288 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1289 log("pass is using the current design as mapping library.\n");
1291 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1292 log("flattened by this command.\n");
1295 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1298 void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
1300 log_header(design
, "Executing FLATTEN pass (flatten design).\n");
1303 TechmapWorker worker
;
1304 worker
.flatten_mode
= true;
1307 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
1308 if (args
[argidx
] == "-wb") {
1309 worker
.ignore_wb
= true;
1314 extra_args(args
, argidx
, design
);
1317 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
, RTLIL::sort_by_id_str
>> celltypeMap
;
1318 for (auto module
: design
->modules())
1319 celltypeMap
[module
->name
].insert(module
->name
);
1321 RTLIL::Module
*top_mod
= NULL
;
1322 if (design
->full_selection())
1323 for (auto mod
: design
->modules())
1324 if (mod
->get_bool_attribute(ID(top
)))
1327 std::set
<RTLIL::Cell
*> handled_cells
;
1328 if (top_mod
!= NULL
) {
1329 worker
.flatten_do_list
.insert(top_mod
->name
);
1330 while (!worker
.flatten_do_list
.empty()) {
1331 auto mod
= design
->module(*worker
.flatten_do_list
.begin());
1332 while (worker
.techmap_module(design
, mod
, design
, handled_cells
, celltypeMap
, false)) { }
1333 worker
.flatten_done_list
.insert(mod
->name
);
1334 worker
.flatten_do_list
.erase(mod
->name
);
1337 for (auto mod
: vector
<Module
*>(design
->modules())) {
1338 while (worker
.techmap_module(design
, mod
, design
, handled_cells
, celltypeMap
, false)) { }
1343 log("No more expansions possible.\n");
1345 if (top_mod
!= NULL
)
1347 pool
<RTLIL::IdString
> used_modules
, new_used_modules
;
1348 new_used_modules
.insert(top_mod
->name
);
1349 while (!new_used_modules
.empty()) {
1350 pool
<RTLIL::IdString
> queue
;
1351 queue
.swap(new_used_modules
);
1352 for (auto modname
: queue
)
1353 used_modules
.insert(modname
);
1354 for (auto modname
: queue
)
1355 for (auto cell
: design
->module(modname
)->cells())
1356 if (design
->module(cell
->type
) && !used_modules
[cell
->type
])
1357 new_used_modules
.insert(cell
->type
);
1360 dict
<RTLIL::IdString
, RTLIL::Module
*> new_modules
;
1361 for (auto mod
: vector
<Module
*>(design
->modules()))
1362 if (used_modules
[mod
->name
] || mod
->get_blackbox_attribute(worker
.ignore_wb
)) {
1363 new_modules
[mod
->name
] = mod
;
1365 log("Deleting now unused module %s.\n", log_id(mod
));
1368 design
->modules_
.swap(new_modules
);
1375 PRIVATE_NAMESPACE_END