2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/log.h"
27 #include "passes/techmap/stdcells.inc"
29 static void apply_prefix(std::string prefix
, std::string
&id
)
32 id
= prefix
+ "." + id
.substr(1);
34 id
= "$techmap" + prefix
+ "." + id
;
37 static void apply_prefix(std::string prefix
, RTLIL::SigSpec
&sig
, RTLIL::Module
*module
)
39 for (size_t i
= 0; i
< sig
.chunks
.size(); i
++) {
40 if (sig
.chunks
[i
].wire
== NULL
)
42 std::string wire_name
= sig
.chunks
[i
].wire
->name
;
43 apply_prefix(prefix
, wire_name
);
44 assert(module
->wires
.count(wire_name
) > 0);
45 sig
.chunks
[i
].wire
= module
->wires
[wire_name
];
49 std::map
<std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>>, RTLIL::Module
*> techmap_cache
;
50 std::map
<RTLIL::Module
*, bool> techmap_fail_cache
;
52 static bool techmap_fail_check(RTLIL::Module
*module
)
57 if (techmap_fail_cache
.count(module
) > 0)
58 return techmap_fail_cache
.at(module
);
60 for (auto &it
: module
->wires
) {
61 std::string name
= it
.first
;
62 if (name
== "\\TECHMAP_FAIL")
63 return techmap_fail_cache
[module
] = true;
64 if (name
.size() > 13 && name
[0] == '\\' && name
.substr(name
.size()-13) == ".TECHMAP_FAIL")
65 return techmap_fail_cache
[module
] = true;
68 return techmap_fail_cache
[module
] = false;
71 static void techmap_module_worker(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Cell
*cell
, RTLIL::Module
*tpl
)
73 log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module
->name
), RTLIL::id2cstr(cell
->name
), RTLIL::id2cstr(tpl
->name
));
75 if (tpl
->memories
.size() != 0)
76 log_error("Technology map yielded memories -> this is not supported.");
78 if (tpl
->processes
.size() != 0)
79 log_error("Technology map yielded processes -> this is not supported.");
81 for (auto &it
: tpl
->wires
) {
82 RTLIL::Wire
*w
= new RTLIL::Wire(*it
.second
);
83 apply_prefix(cell
->name
, w
->name
);
84 w
->port_input
= false;
85 w
->port_output
= false;
87 module
->wires
[w
->name
] = w
;
88 design
->select(module
, w
);
91 for (auto &it
: tpl
->cells
) {
92 RTLIL::Cell
*c
= new RTLIL::Cell(*it
.second
);
93 if (c
->type
.substr(0, 2) == "\\$")
94 c
->type
= c
->type
.substr(1);
95 apply_prefix(cell
->name
, c
->name
);
96 for (auto &it2
: c
->connections
)
97 apply_prefix(cell
->name
, it2
.second
, module
);
98 module
->cells
[c
->name
] = c
;
99 design
->select(module
, c
);
102 for (auto &it
: tpl
->connections
) {
103 RTLIL::SigSig c
= it
;
104 apply_prefix(cell
->name
, c
.first
, module
);
105 apply_prefix(cell
->name
, c
.second
, module
);
106 module
->connections
.push_back(c
);
109 for (auto &it
: cell
->connections
) {
110 if (tpl
->wires
.count(it
.first
) == 0 || tpl
->wires
.at(it
.first
)->port_id
== 0)
112 RTLIL::Wire
*w
= tpl
->wires
[it
.first
];
114 if (w
->port_output
) {
116 c
.second
= RTLIL::SigSpec(w
);
117 apply_prefix(cell
->name
, c
.second
, module
);
119 c
.first
= RTLIL::SigSpec(w
);
120 c
.second
= it
.second
;
121 apply_prefix(cell
->name
, c
.first
, module
);
123 if (c
.second
.width
> c
.first
.width
)
124 c
.second
.remove(c
.first
.width
, c
.second
.width
- c
.first
.width
);
125 if (c
.second
.width
< c
.first
.width
)
126 c
.second
.append(RTLIL::SigSpec(RTLIL::State::S0
, c
.first
.width
- c
.second
.width
));
127 assert(c
.first
.width
== c
.second
.width
);
128 module
->connections
.push_back(c
);
131 module
->cells
.erase(cell
->name
);
135 static bool techmap_module(RTLIL::Design
*design
, RTLIL::Module
*module
, RTLIL::Design
*map
, std::set
<RTLIL::Cell
*> &handled_cells
,
136 const std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
>> &celltypeMap
)
138 if (!design
->selected(module
))
141 bool did_something
= false;
143 std::vector
<std::string
> cell_names
;
145 for (auto &cell_it
: module
->cells
)
146 cell_names
.push_back(cell_it
.first
);
148 for (auto &cell_name
: cell_names
)
150 if (module
->cells
.count(cell_name
) == 0)
153 RTLIL::Cell
*cell
= module
->cells
[cell_name
];
155 if (!design
->selected(module
, cell
) || handled_cells
.count(cell
) > 0)
158 if (celltypeMap
.count(cell
->type
) == 0)
161 for (auto &tpl_name
: celltypeMap
.at(cell
->type
))
163 std::string derived_name
= tpl_name
;
164 RTLIL::Module
*tpl
= map
->modules
[tpl_name
];
165 std::map
<RTLIL::IdString
, RTLIL::Const
> parameters
= cell
->parameters
;
167 for (auto conn
: cell
->connections
) {
168 if (tpl
->wires
.count(conn
.first
) > 0 && tpl
->wires
.at(conn
.first
)->port_id
> 0)
170 if (!conn
.second
.is_fully_const() || parameters
.count(conn
.first
) > 0)
172 parameters
[conn
.first
] = conn
.second
.as_const();
180 std::pair
<RTLIL::IdString
, std::map
<RTLIL::IdString
, RTLIL::Const
>> key(tpl_name
, parameters
);
181 if (techmap_cache
.count(key
) > 0) {
182 tpl
= techmap_cache
[key
];
184 if (cell
->parameters
.size() != 0) {
185 derived_name
= tpl
->derive(map
, parameters
);
186 tpl
= map
->modules
[derived_name
];
187 log_header("Continuing TECHMAP pass.\n");
189 techmap_cache
[key
] = tpl
;
192 if (techmap_fail_check(tpl
)) {
193 log("Not using module `%s' from techmap as it contains a TECHMAP_FAIL marker wire.\n", derived_name
.c_str());
197 techmap_module_worker(design
, module
, cell
, tpl
);
198 did_something
= true;
203 handled_cells
.insert(cell
);
206 return did_something
;
209 struct TechmapPass
: public Pass
{
210 TechmapPass() : Pass("techmap", "simple technology mapper") { }
213 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
215 log(" techmap [-map filename] [selection]\n");
217 log("This pass implements a very simple technology mapper that replaces cells in\n");
218 log("the design with implementations given in form of a verilog or ilang source\n");
221 log(" -map filename\n");
222 log(" the library of cell implementations to be used.\n");
223 log(" without this parameter a builtin library is used that\n");
224 log(" transforms the internal RTL cells to the internal gate\n");
227 log("When a module in the map file has the 'celltype' attribute set, it will match\n");
228 log("cells with a type that match the text value of this attribute.\n");
230 log("When a module in the map file contains a wire with the name 'TECHMAP_FAIL' (or\n");
231 log("one matching '*.TECHMAP_FAIL') then no substitution will be performed. The\n");
232 log("modules in the map file are tried in alphabetical order.\n");
234 log("When a module in the map file has a parameter where the according cell in the\n");
235 log("design has a port, the module from the map file is only used if the port in\n");
236 log("the design is connected to a constant value. The parameter is then set to the\n");
237 log("constant value.\n");
239 log("See 'help extract' for a pass that does the opposite thing.\n");
241 log("See 'help flatten' for a pass that does flatten the design (which is\n");
242 log("esentially techmap but using the design itself as map library).\n");
245 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
247 log_header("Executing TECHMAP pass (map to technology primitives).\n");
250 std::string filename
;
253 for (argidx
= 1; argidx
< args
.size(); argidx
++) {
254 if (args
[argidx
] == "-map" && argidx
+1 < args
.size()) {
255 filename
= args
[++argidx
];
260 extra_args(args
, argidx
, design
);
262 FILE *f
= filename
.empty() ? fmemopen(stdcells_code
, strlen(stdcells_code
), "rt") : fopen(filename
.c_str(), "rt");
264 log_cmd_error("Can't open map file `%s'\n", filename
.c_str());
266 RTLIL::Design
*map
= new RTLIL::Design
;
267 Frontend::frontend_call(map
, f
, filename
.empty() ? "<stdcells.v>" : filename
,
268 (filename
.size() > 3 && filename
.substr(filename
.size()-3) == ".il") ? "ilang" : "verilog");
272 std::map
<RTLIL::IdString
, RTLIL::Module
*> modules_new
;
273 for (auto &it
: map
->modules
) {
274 if (it
.first
.substr(0, 2) == "\\$")
275 it
.second
->name
= it
.first
.substr(1);
276 modules_new
[it
.second
->name
] = it
.second
;
278 map
->modules
.swap(modules_new
);
280 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
>> celltypeMap
;
281 for (auto &it
: map
->modules
) {
282 if (it
.second
->attributes
.count("\\celltype") && !it
.second
->attributes
.at("\\celltype").str
.empty()) {
283 celltypeMap
[RTLIL::escape_id(it
.second
->attributes
.at("\\celltype").str
)].insert(it
.first
);
285 celltypeMap
[it
.first
].insert(it
.first
);
288 bool did_something
= true;
289 std::set
<RTLIL::Cell
*> handled_cells
;
290 while (did_something
) {
291 did_something
= false;
292 for (auto &mod_it
: design
->modules
)
293 if (techmap_module(design
, mod_it
.second
, map
, handled_cells
, celltypeMap
))
294 did_something
= true;
297 log("No more expansions possible.\n");
298 techmap_cache
.clear();
299 techmap_fail_cache
.clear();
305 struct FlattenPass
: public Pass
{
306 FlattenPass() : Pass("flatten", "flatten design") { }
309 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
311 log(" flatten [selection]\n");
313 log("This pass flattens the design by replacing cells by their implementation. This\n");
314 log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
315 log("pass is using the current design as mapping library.\n");
318 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
320 log_header("Executing FLATTEN pass (flatten design).\n");
323 extra_args(args
, 1, design
);
325 std::map
<RTLIL::IdString
, std::set
<RTLIL::IdString
>> celltypeMap
;
326 for (auto &it
: design
->modules
)
327 celltypeMap
[it
.first
].insert(it
.first
);
329 bool did_something
= true;
330 std::set
<RTLIL::Cell
*> handled_cells
;
331 while (did_something
) {
332 did_something
= false;
333 for (auto &mod_it
: design
->modules
)
334 if (techmap_module(design
, mod_it
.second
, design
, handled_cells
, celltypeMap
))
335 did_something
= true;
338 log("No more expansions possible.\n");
339 techmap_cache
.clear();
340 techmap_fail_cache
.clear();