projects / yosys.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
[yosys.git] / passes / techmap / techmap.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/yosys.h"
21 #include "kernel/utils.h"
22 #include "kernel/sigtools.h"
23 #include "libs/sha1/sha1.h"
24
25 #include <stdlib.h>
26 #include <stdio.h>
27 #include <string.h>
28
29 #include "simplemap.h"
30 #include "passes/techmap/techmap.inc"
31
32 YOSYS_NAMESPACE_BEGIN
33
34 // see maccmap.cc
35 extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false);
36
37 YOSYS_NAMESPACE_END
38
39 USING_YOSYS_NAMESPACE
40 PRIVATE_NAMESPACE_BEGIN
41
42 void apply_prefix(IdString prefix, IdString &id)
43 {
44 if (id[0] == '\\')
45 id = stringf("%s.%s", prefix.c_str(), id.c_str()+1);
46 else
47 id = stringf("$techmap%s.%s", prefix.c_str(), id.c_str());
48 }
49
50 void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
51 {
52 vector<SigChunk> chunks = sig;
53 for (auto &chunk : chunks)
54 if (chunk.wire != NULL) {
55 IdString wire_name = chunk.wire->name;
56 apply_prefix(prefix, wire_name);
57 log_assert(module->wires_.count(wire_name) > 0);
58 chunk.wire = module->wires_[wire_name];
59 }
60 sig = chunks;
61 }
62
63 struct TechmapWorker
64 {
65 std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
66 std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
67 std::map<RTLIL::Module*, bool> techmap_do_cache;
68 std::set<RTLIL::Module*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Module>> module_queue;
69 dict<Module*, SigMap> sigmaps;
70
71 pool<IdString> flatten_do_list;
72 pool<IdString> flatten_done_list;
73 pool<Cell*> flatten_keep_list;
74
75 pool<string> log_msg_cache;
76
77 struct TechmapWireData {
78 RTLIL::Wire *wire;
79 RTLIL::SigSpec value;
80 };
81
82 typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
83
84 bool extern_mode;
85 bool assert_mode;
86 bool flatten_mode;
87 bool recursive_mode;
88 bool autoproc_mode;
89 bool ignore_wb;
90
91 TechmapWorker()
92 {
93 extern_mode = false;
94 assert_mode = false;
95 flatten_mode = false;
96 recursive_mode = false;
97 autoproc_mode = false;
98 ignore_wb = false;
99 }
100
101 std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
102 {
103 std::string constmap_info;
104 std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
105
106 for (auto conn : cell->connections())
107 for (int i = 0; i < GetSize(conn.second); i++) {
108 RTLIL::SigBit bit = sigmap(conn.second[i]);
109 if (bit.wire == nullptr) {
110 if (verbose)
111 log(" Constant input on bit %d of port %s: %s\n", i, log_id(conn.first), log_signal(bit));
112 constmap_info += stringf("|%s %d %d", log_id(conn.first), i, bit.data);
113 } else if (connbits_map.count(bit)) {
114 if (verbose)
115 log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
116 connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
117 constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
118 log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
119 } else {
120 connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);
121 constmap_info += stringf("|%s %d", log_id(conn.first), i);
122 }
123 }
124
125 return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
126 }
127
128 TechmapWires techmap_find_special_wires(RTLIL::Module *module)
129 {
130 TechmapWires result;
131
132 if (module == NULL)
133 return result;
134
135 for (auto &it : module->wires_) {
136 const char *p = it.first.c_str();
137 if (*p == '$')
138 continue;
139
140 const char *q = strrchr(p+1, '.');
141 p = q ? q+1 : p+1;
142
143 if (!strncmp(p, "_TECHMAP_", 9)) {
144 TechmapWireData record;
145 record.wire = it.second;
146 record.value = it.second;
147 result[p].push_back(record);
148 it.second->attributes[ID::keep] = RTLIL::Const(1);
149 it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
150 }
151 }
152
153 if (!result.empty()) {
154 SigMap sigmap(module);
155 for (auto &it1 : result)
156 for (auto &it2 : it1.second)
157 sigmap.apply(it2.value);
158 }
159
160 return result;
161 }
162
163 void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
164 {
165 if (tpl->processes.size() != 0) {
166 log("Technology map yielded processes:");
167 for (auto &it : tpl->processes)
168 log(" %s",RTLIL::id2cstr(it.first));
169 log("\n");
170 if (autoproc_mode) {
171 Pass::call_on_module(tpl->design, tpl, "proc");
172 log_assert(GetSize(tpl->processes) == 0);
173 } else
174 log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
175 }
176
177 std::string orig_cell_name;
178 pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
179
180 if (!flatten_mode) {
181 for (auto &it : tpl->cells_)
182 if (it.first == ID(_TECHMAP_REPLACE_)) {
183 orig_cell_name = cell->name.str();
184 module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
185 break;
186 }
187 }
188
189 dict<IdString, IdString> memory_renames;
190
191 for (auto &it : tpl->memories) {
192 IdString m_name = it.first;
193 apply_prefix(cell->name, m_name);
194 RTLIL::Memory *m = new RTLIL::Memory;
195 m->name = m_name;
196 m->width = it.second->width;
197 m->start_offset = it.second->start_offset;
198 m->size = it.second->size;
199 m->attributes = it.second->attributes;
200 if (m->attributes.count(ID(src)))
201 m->add_strpool_attribute(ID(src), extra_src_attrs);
202 module->memories[m->name] = m;
203 memory_renames[it.first] = m->name;
204 design->select(module, m);
205 }
206
207 std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
208 dict<Wire*, IdString> temp_renamed_wires;
209
210 for (auto &it : tpl->wires_) {
211 if (it.second->port_id > 0)
212 positional_ports[stringf("$%d", it.second->port_id)] = it.first;
213 IdString w_name = it.second->name;
214 apply_prefix(cell->name, w_name);
215 RTLIL::Wire *w = module->wire(w_name);
216 if (w != nullptr) {
217 if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
218 temp_renamed_wires[w] = w->name;
219 module->rename(w, NEW_ID);
220 w = nullptr;
221 } else {
222 w->attributes.erase(ID(hierconn));
223 if (GetSize(w) < GetSize(it.second)) {
224 log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
225 log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
226 w->width = GetSize(it.second);
227 }
228 }
229 }
230 if (w == nullptr) {
231 w = module->addWire(w_name, it.second);
232 w->port_input = false;
233 w->port_output = false;
234 w->port_id = 0;
235 if (it.second->get_bool_attribute(ID(_techmap_special_)))
236 w->attributes.clear();
237 if (w->attributes.count(ID(src)))
238 w->add_strpool_attribute(ID(src), extra_src_attrs);
239 }
240 design->select(module, w);
241 }
242
243 SigMap tpl_sigmap(tpl);
244 pool<SigBit> tpl_written_bits;
245
246 for (auto &it1 : tpl->cells_)
247 for (auto &it2 : it1.second->connections_)
248 if (it1.second->output(it2.first))
249 for (auto bit : tpl_sigmap(it2.second))
250 tpl_written_bits.insert(bit);
251 for (auto &it1 : tpl->connections_)
252 for (auto bit : tpl_sigmap(it1.first))
253 tpl_written_bits.insert(bit);
254
255 SigMap port_signal_map;
256 SigSig port_signal_assign;
257
258 for (auto &it : cell->connections())
259 {
260 RTLIL::IdString portname = it.first;
261 if (positional_ports.count(portname) > 0)
262 portname = positional_ports.at(portname);
263 if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
264 if (portname.begins_with("$"))
265 log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
266 continue;
267 }
268
269 if (GetSize(it.second) == 0)
270 continue;
271
272 RTLIL::Wire *w = tpl->wires_.at(portname);
273 RTLIL::SigSig c, extra_connect;
274
275 if (w->port_output && !w->port_input) {
276 c.first = it.second;
277 c.second = RTLIL::SigSpec(w);
278 apply_prefix(cell->name, c.second, module);
279 extra_connect.first = c.second;
280 extra_connect.second = c.first;
281 } else if (!w->port_output && w->port_input) {
282 c.first = RTLIL::SigSpec(w);
283 c.second = it.second;
284 apply_prefix(cell->name, c.first, module);
285 extra_connect.first = c.first;
286 extra_connect.second = c.second;
287 } else {
288 SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
289 apply_prefix(cell->name, sig_tpl_pf, module);
290 for (int i = 0; i < GetSize(sig_tpl) && i < GetSize(sig_mod); i++) {
291 if (tpl_written_bits.count(tpl_sigmap(sig_tpl[i]))) {
292 c.first.append(sig_mod[i]);
293 c.second.append(sig_tpl_pf[i]);
294 } else {
295 c.first.append(sig_tpl_pf[i]);
296 c.second.append(sig_mod[i]);
297 }
298 }
299 extra_connect.first = sig_tpl_pf;
300 extra_connect.second = sig_mod;
301 }
302
303 if (c.second.size() > c.first.size())
304 c.second.remove(c.first.size(), c.second.size() - c.first.size());
305
306 if (c.second.size() < c.first.size())
307 c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
308
309 log_assert(c.first.size() == c.second.size());
310
311 if (flatten_mode)
312 {
313 // more conservative approach:
314 // connect internal and external wires
315
316 if (sigmaps.count(module) == 0)
317 sigmaps[module].set(module);
318
319 if (sigmaps.at(module)(c.first).has_const())
320 log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
321 log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
322
323 module->connect(c);
324 }
325 else
326 {
327 // approach that yields nicer outputs:
328 // replace internal wires that are connected to external wires
329
330 if (w->port_output && !w->port_input) {
331 port_signal_map.add(c.second, c.first);
332 } else
333 if (!w->port_output && w->port_input) {
334 port_signal_map.add(c.first, c.second);
335 } else {
336 module->connect(c);
337 extra_connect = SigSig();
338 }
339
340 for (auto &attr : w->attributes) {
341 if (attr.first == ID(src))
342 continue;
343 module->connect(extra_connect);
344 break;
345 }
346 }
347 }
348
349 for (auto &it : tpl->cells_)
350 {
351 IdString c_name = it.second->name.str();
352 bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
353
354 if (techmap_replace_cell)
355 c_name = orig_cell_name;
356 else
357 apply_prefix(cell->name, c_name);
358
359 RTLIL::Cell *c = module->addCell(c_name, it.second);
360 design->select(module, c);
361
362 if (!flatten_mode && c->type.begins_with("\\$"))
363 c->type = c->type.substr(1);
364
365 for (auto &it2 : c->connections_) {
366 apply_prefix(cell->name, it2.second, module);
367 port_signal_map.apply(it2.second);
368 }
369
370 if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
371 IdString memid = c->getParam(ID(MEMID)).decode_string();
372 log_assert(memory_renames.count(memid) != 0);
373 c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
374 }
375
376 if (c->type == ID($mem)) {
377 IdString memid = c->getParam(ID(MEMID)).decode_string();
378 apply_prefix(cell->name, memid);
379 c->setParam(ID(MEMID), Const(memid.c_str()));
380 }
381
382 if (c->attributes.count(ID(src)))
383 c->add_strpool_attribute(ID(src), extra_src_attrs);
384
385 if (techmap_replace_cell)
386 for (auto attr : cell->attributes)
387 if (!c->attributes.count(attr.first))
388 c->attributes[attr.first] = attr.second;
389 }
390
391 for (auto &it : tpl->connections()) {
392 RTLIL::SigSig c = it;
393 apply_prefix(cell->name.str(), c.first, module);
394 apply_prefix(cell->name.str(), c.second, module);
395 port_signal_map.apply(c.first);
396 port_signal_map.apply(c.second);
397 module->connect(c);
398 }
399
400 module->remove(cell);
401
402 for (auto &it : temp_renamed_wires)
403 {
404 Wire *w = it.first;
405 IdString name = it.second;
406 IdString altname = module->uniquify(name);
407 Wire *other_w = module->wire(name);
408 module->rename(other_w, altname);
409 module->rename(w, name);
410 }
411 }
412
413 bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
414 const std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> &celltypeMap, bool in_recursion)
415 {
416 std::string mapmsg_prefix = in_recursion ? "Recursively mapping" : "Mapping";
417
418 if (!design->selected(module) || module->get_blackbox_attribute(ignore_wb))
419 return false;
420
421 bool log_continue = false;
422 bool did_something = false;
423 LogMakeDebugHdl mkdebug;
424
425 SigMap sigmap(module);
426
427 dict<SigBit, State> init_bits;
428 pool<SigBit> remove_init_bits;
429
430 for (auto wire : module->wires()) {
431 if (wire->attributes.count("\\init")) {
432 Const value = wire->attributes.at("\\init");
433 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
434 if (value[i] != State::Sx)
435 init_bits[sigmap(SigBit(wire, i))] = value[i];
436 }
437 }
438
439 TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
440 std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
441 std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
442
443 for (auto cell : module->cells())
444 {
445 if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
446 continue;
447
448 std::string cell_type = cell->type.str();
449 if (in_recursion && cell->type.begins_with("\\$"))
450 cell_type = cell_type.substr(1);
451
452 if (celltypeMap.count(cell_type) == 0) {
453 if (assert_mode && cell_type.back() != '_')
454 log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
455 continue;
456 }
457
458 if (flatten_mode) {
459 bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
460 for (auto &tpl_name : celltypeMap.at(cell_type))
461 if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
462 keepit = true;
463 if (keepit) {
464 if (!flatten_keep_list[cell]) {
465 log("Keeping %s.%s (found keep_hierarchy property).\n", log_id(module), log_id(cell));
466 flatten_keep_list.insert(cell);
467 }
468 if (!flatten_done_list[cell->type])
469 flatten_do_list.insert(cell->type);
470 continue;
471 }
472 }
473
474 for (auto &conn : cell->connections())
475 {
476 RTLIL::SigSpec sig = sigmap(conn.second);
477 sig.remove_const();
478
479 if (GetSize(sig) == 0)
480 continue;
481
482 for (auto &tpl_name : celltypeMap.at(cell_type)) {
483 RTLIL::Module *tpl = map->modules_[tpl_name];
484 RTLIL::Wire *port = tpl->wire(conn.first);
485 if (port && port->port_input)
486 cell_to_inbit[cell].insert(sig.begin(), sig.end());
487 if (port && port->port_output)
488 for (auto &bit : sig)
489 outbit_to_cell[bit].insert(cell);
490 }
491 }
492
493 cells.node(cell);
494 }
495
496 for (auto &it_right : cell_to_inbit)
497 for (auto &it_sigbit : it_right.second)
498 for (auto &it_left : outbit_to_cell[it_sigbit])
499 cells.edge(it_left, it_right.first);
500
501 cells.sort();
502
503 for (auto cell : cells.sorted)
504 {
505 log_assert(handled_cells.count(cell) == 0);
506 log_assert(cell == module->cell(cell->name));
507 bool mapped_cell = false;
508
509 std::string cell_type = cell->type.str();
510
511 if (in_recursion && cell->type.begins_with("\\$"))
512 cell_type = cell_type.substr(1);
513
514 for (auto &tpl_name : celltypeMap.at(cell_type))
515 {
516 RTLIL::IdString derived_name = tpl_name;
517 RTLIL::Module *tpl = map->modules_[tpl_name];
518 std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
519
520 if (tpl->get_blackbox_attribute(ignore_wb))
521 continue;
522
523 if (!flatten_mode)
524 {
525 std::string extmapper_name;
526
527 if (tpl->get_bool_attribute(ID(techmap_simplemap)))
528 extmapper_name = "simplemap";
529
530 if (tpl->get_bool_attribute(ID(techmap_maccmap)))
531 extmapper_name = "maccmap";
532
533 if (tpl->attributes.count(ID(techmap_wrap)))
534 extmapper_name = "wrap";
535
536 if (!extmapper_name.empty())
537 {
538 cell->type = cell_type;
539
540 if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
541 {
542 std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
543
544 for (auto &c : cell->parameters)
545 m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
546
547 if (extmapper_name == "wrap")
548 m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
549
550 RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
551 RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
552
553 if (extmapper_module == nullptr)
554 {
555 extmapper_module = extmapper_design->addModule(m_name);
556 RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
557
558 extmapper_cell->set_src_attribute(cell->get_src_attribute());
559
560 int port_counter = 1;
561 for (auto &c : extmapper_cell->connections_) {
562 RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
563 if (w->name.in(ID::Y, ID(Q)))
564 w->port_output = true;
565 else
566 w->port_input = true;
567 w->port_id = port_counter++;
568 c.second = w;
569 }
570
571 extmapper_module->fixup_ports();
572 extmapper_module->check();
573
574 if (extmapper_name == "simplemap") {
575 log("Creating %s with simplemap.\n", log_id(extmapper_module));
576 if (simplemap_mappers.count(extmapper_cell->type) == 0)
577 log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
578 simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
579 extmapper_module->remove(extmapper_cell);
580 }
581
582 if (extmapper_name == "maccmap") {
583 log("Creating %s with maccmap.\n", log_id(extmapper_module));
584 if (extmapper_cell->type != ID($macc))
585 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
586 maccmap(extmapper_module, extmapper_cell);
587 extmapper_module->remove(extmapper_cell);
588 }
589
590 if (extmapper_name == "wrap") {
591 std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
592 log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
593 mkdebug.on();
594 Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
595 log_continue = true;
596 }
597 }
598
599 cell->type = extmapper_module->name;
600 cell->parameters.clear();
601
602 if (!extern_mode || in_recursion) {
603 tpl = extmapper_module;
604 goto use_wrapper_tpl;
605 }
606
607 auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
608 if (!log_msg_cache.count(msg)) {
609 log_msg_cache.insert(msg);
610 log("%s\n", msg.c_str());
611 }
612 log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
613 }
614 else
615 {
616 auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
617 if (!log_msg_cache.count(msg)) {
618 log_msg_cache.insert(msg);
619 log("%s\n", msg.c_str());
620 }
621 log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
622
623 if (extmapper_name == "simplemap") {
624 if (simplemap_mappers.count(cell->type) == 0)
625 log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
626 simplemap_mappers.at(cell->type)(module, cell);
627 }
628
629 if (extmapper_name == "maccmap") {
630 if (cell->type != ID($macc))
631 log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
632 maccmap(module, cell);
633 }
634
635 module->remove(cell);
636 cell = NULL;
637 }
638
639 did_something = true;
640 mapped_cell = true;
641 break;
642 }
643
644 for (auto conn : cell->connections()) {
645 if (conn.first.begins_with("$"))
646 continue;
647 if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
648 continue;
649 if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
650 goto next_tpl;
651 parameters[conn.first] = conn.second.as_const();
652 }
653
654 if (0) {
655 next_tpl:
656 continue;
657 }
658
659 if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
660 parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
661
662 for (auto conn : cell->connections()) {
663 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
664 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
665 for (auto &bit : v)
666 bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
667 parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
668 }
669 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
670 std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
671 for (auto &bit : v)
672 if (bit.wire != NULL)
673 bit = RTLIL::SigBit(RTLIL::State::Sx);
674 parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
675 }
676 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))) != 0) {
677 auto sig = sigmap(conn.second);
678 RTLIL::Const value(State::Sx, sig.size());
679 for (int i = 0; i < sig.size(); i++) {
680 auto it = init_bits.find(sig[i]);
681 if (it != init_bits.end()) {
682 value[i] = it->second;
683 }
684 }
685 parameters[stringf("\\_TECHMAP_WIREINIT_%s_", RTLIL::id2cstr(conn.first))] = value;
686 }
687 }
688
689 int unique_bit_id_counter = 0;
690 std::map<RTLIL::SigBit, int> unique_bit_id;
691 unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
692 unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
693 unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
694 unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
695
696 for (auto conn : cell->connections())
697 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
698 for (auto &bit : sigmap(conn.second).to_sigbit_vector())
699 if (unique_bit_id.count(bit) == 0)
700 unique_bit_id[bit] = unique_bit_id_counter++;
701 }
702
703 // Find highest bit set
704 int bits = 0;
705 for (int i = 0; i < 32; i++)
706 if (((unique_bit_id_counter-1) & (1 << i)) != 0)
707 bits = i;
708 // Increment index by one to get number of bits
709 bits++;
710 if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
711 parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
712
713 for (auto conn : cell->connections())
714 if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
715 RTLIL::Const value;
716 for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
717 RTLIL::Const chunk(unique_bit_id.at(bit), bits);
718 value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
719 }
720 parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
721 }
722 }
723
724 if (0) {
725 use_wrapper_tpl:;
726 // do not register techmap_wrap modules with techmap_cache
727 } else {
728 std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
729 if (techmap_cache.count(key) > 0) {
730 tpl = techmap_cache[key];
731 } else {
732 if (parameters.size() != 0) {
733 mkdebug.on();
734 derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
735 tpl = map->module(derived_name);
736 log_continue = true;
737 }
738 techmap_cache[key] = tpl;
739 }
740 }
741
742 if (flatten_mode) {
743 techmap_do_cache[tpl] = true;
744 } else {
745 RTLIL::Module *constmapped_tpl = map->module(constmap_tpl_name(sigmap, tpl, cell, false));
746 if (constmapped_tpl != nullptr)
747 tpl = constmapped_tpl;
748 }
749
750 if (techmap_do_cache.count(tpl) == 0)
751 {
752 bool keep_running = true;
753 techmap_do_cache[tpl] = true;
754
755 std::set<std::string> techmap_wire_names;
756
757 while (keep_running)
758 {
759 TechmapWires twd = techmap_find_special_wires(tpl);
760 keep_running = false;
761
762 for (auto &it : twd)
763 techmap_wire_names.insert(it.first);
764
765 for (auto &it : twd["_TECHMAP_FAIL_"]) {
766 RTLIL::SigSpec value = it.value;
767 if (value.is_fully_const() && value.as_bool()) {
768 log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
769 derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
770 techmap_do_cache[tpl] = false;
771 }
772 }
773
774 if (!techmap_do_cache[tpl])
775 break;
776
777 for (auto &it : twd)
778 {
779 if (it.first.compare(0, 12, "_TECHMAP_DO_") != 0 || it.second.empty())
780 continue;
781
782 auto &data = it.second.front();
783
784 if (!data.value.is_fully_const())
785 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
786
787 techmap_wire_names.erase(it.first);
788
789 const char *p = data.wire->name.c_str();
790 const char *q = strrchr(p+1, '.');
791 q = q ? q : p+1;
792
793 std::string cmd_string = data.value.as_const().decode_string();
794
795 restart_eval_cmd_string:
796 if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
797 {
798 cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
799
800 log("Analyzing pattern of constant bits for this cell:\n");
801 RTLIL::IdString new_tpl_name = constmap_tpl_name(sigmap, tpl, cell, true);
802 log("Creating constmapped module `%s'.\n", log_id(new_tpl_name));
803 log_assert(map->module(new_tpl_name) == nullptr);
804
805 RTLIL::Module *new_tpl = map->addModule(new_tpl_name);
806 tpl->cloneInto(new_tpl);
807
808 techmap_do_cache.erase(tpl);
809 techmap_do_cache[new_tpl] = true;
810 tpl = new_tpl;
811
812 std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
813 std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
814 std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
815
816 for (auto wire : tpl->wires().to_vector())
817 {
818 if (!wire->port_input || wire->port_output)
819 continue;
820
821 RTLIL::IdString port_name = wire->name;
822 tpl->rename(wire, NEW_ID);
823
824 RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
825 wire->port_input = false;
826 wire->port_id = 0;
827
828 for (int i = 0; i < wire->width; i++) {
829 port_new2old_map[RTLIL::SigBit(new_wire, i)] = RTLIL::SigBit(wire, i);
830 port_connmap[RTLIL::SigBit(wire, i)] = RTLIL::SigBit(new_wire, i);
831 }
832 }
833
834 for (auto conn : cell->connections())
835 for (int i = 0; i < GetSize(conn.second); i++)
836 {
837 RTLIL::SigBit bit = sigmap(conn.second[i]);
838 RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
839
840 if (bit.wire == nullptr)
841 {
842 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
843 port_connmap.at(oldbit) = bit;
844 }
845 else if (cellbits_to_tplbits.count(bit))
846 {
847 RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
848 port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
849 }
850 else
851 cellbits_to_tplbits[bit] = tplbit;
852 }
853
854 RTLIL::SigSig port_conn;
855 for (auto &it : port_connmap) {
856 port_conn.first.append_bit(it.first);
857 port_conn.second.append_bit(it.second);
858 }
859 tpl->connect(port_conn);
860
861 tpl->check();
862 goto restart_eval_cmd_string;
863 }
864
865 if (cmd_string.rfind("RECURSION; ", 0) == 0)
866 {
867 cmd_string = cmd_string.substr(strlen("RECURSION; "));
868 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
869 goto restart_eval_cmd_string;
870 }
871
872 Pass::call_on_module(map, tpl, cmd_string);
873
874 log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
875 std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
876 while (tpl->wires_.count(new_name))
877 new_name += "_";
878 tpl->rename(data.wire->name, new_name);
879
880 keep_running = true;
881 break;
882 }
883 }
884
885 TechmapWires twd = techmap_find_special_wires(tpl);
886 for (auto &it : twd) {
887 if (it.first != "_TECHMAP_FAIL_" && (it.first.substr(0, 20) != "_TECHMAP_REMOVEINIT_" || it.first[it.first.size()-1] != '_') && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
888 log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
889 if (techmap_do_cache[tpl])
890 for (auto &it2 : it.second)
891 if (!it2.value.is_fully_const())
892 log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
893 if (it.first.substr(0, 20) == "_TECHMAP_REMOVEINIT_" && techmap_do_cache[tpl]) {
894 for (auto &it2 : it.second) {
895 auto val = it2.value.as_const();
896 auto wirename = RTLIL::escape_id(it.first.substr(20, it.first.size() - 20 - 1));
897 auto it = cell->connections().find(wirename);
898 if (it != cell->connections().end()) {
899 auto sig = sigmap(it->second);
900 for (int i = 0; i < sig.size(); i++)
901 if (val[i] == State::S1)
902 remove_init_bits.insert(sig[i]);
903 }
904 }
905 }
906 techmap_wire_names.erase(it.first);
907 }
908
909 for (auto &it : techmap_wire_names)
910 log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
911
912 if (recursive_mode) {
913 if (log_continue) {
914 log_header(design, "Continuing TECHMAP pass.\n");
915 log_continue = false;
916 mkdebug.off();
917 }
918 while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
919 }
920 }
921
922 if (techmap_do_cache.at(tpl) == false)
923 continue;
924
925 if (log_continue) {
926 log_header(design, "Continuing TECHMAP pass.\n");
927 log_continue = false;
928 mkdebug.off();
929 }
930
931 if (extern_mode && !in_recursion)
932 {
933 std::string m_name = stringf("$extern:%s", log_id(tpl));
934
935 if (!design->module(m_name))
936 {
937 RTLIL::Module *m = design->addModule(m_name);
938 tpl->cloneInto(m);
939
940 for (auto cell : m->cells()) {
941 if (cell->type.begins_with("\\$"))
942 cell->type = cell->type.substr(1);
943 }
944
945 module_queue.insert(m);
946 }
947
948 log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
949 cell->type = m_name;
950 cell->parameters.clear();
951 }
952 else
953 {
954 auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
955 if (!log_msg_cache.count(msg)) {
956 log_msg_cache.insert(msg);
957 log("%s\n", msg.c_str());
958 }
959 log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
960 techmap_module_worker(design, module, cell, tpl);
961 cell = NULL;
962 }
963 did_something = true;
964 mapped_cell = true;
965 break;
966 }
967
968 if (assert_mode && !mapped_cell)
969 log_error("(ASSERT MODE) Failed to map cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
970
971 handled_cells.insert(cell);
972 }
973
974 if (!remove_init_bits.empty()) {
975 for (auto wire : module->wires())
976 if (wire->attributes.count("\\init")) {
977 Const &value = wire->attributes.at("\\init");
978 bool do_cleanup = true;
979 for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
980 SigBit bit = sigmap(SigBit(wire, i));
981 if (remove_init_bits.count(bit))
982 value[i] = State::Sx;
983 else if (value[i] != State::Sx)
984 do_cleanup = false;
985 }
986 if (do_cleanup) {
987 log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
988 wire->attributes.erase("\\init");
989 }
990 }
991 }
992
993 if (log_continue) {
994 log_header(design, "Continuing TECHMAP pass.\n");
995 log_continue = false;
996 mkdebug.off();
997 }
998
999 return did_something;
1000 }
1001 };
1002
1003 struct TechmapPass : public Pass {
1004 TechmapPass() : Pass("techmap", "generic technology mapper") { }
1005 void help() YS_OVERRIDE
1006 {
1007 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1008 log("\n");
1009 log(" techmap [-map filename] [selection]\n");
1010 log("\n");
1011 log("This pass implements a very simple technology mapper that replaces cells in\n");
1012 log("the design with implementations given in form of a Verilog or ilang source\n");
1013 log("file.\n");
1014 log("\n");
1015 log(" -map filename\n");
1016 log(" the library of cell implementations to be used.\n");
1017 log(" without this parameter a builtin library is used that\n");
1018 log(" transforms the internal RTL cells to the internal gate\n");
1019 log(" library.\n");
1020 log("\n");
1021 log(" -map %%<design-name>\n");
1022 log(" like -map above, but with an in-memory design instead of a file.\n");
1023 log("\n");
1024 log(" -extern\n");
1025 log(" load the cell implementations as separate modules into the design\n");
1026 log(" instead of inlining them.\n");
1027 log("\n");
1028 log(" -max_iter <number>\n");
1029 log(" only run the specified number of iterations on each module.\n");
1030 log(" default: unlimited\n");
1031 log("\n");
1032 log(" -recursive\n");
1033 log(" instead of the iterative breadth-first algorithm use a recursive\n");
1034 log(" depth-first algorithm. both methods should yield equivalent results,\n");
1035 log(" but may differ in performance.\n");
1036 log("\n");
1037 log(" -autoproc\n");
1038 log(" Automatically call \"proc\" on implementations that contain processes.\n");
1039 log("\n");
1040 log(" -wb\n");
1041 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1042 log("\n");
1043 log(" -assert\n");
1044 log(" this option will cause techmap to exit with an error if it can't map\n");
1045 log(" a selected cell. only cell types that end on an underscore are accepted\n");
1046 log(" as final cell types by this mode.\n");
1047 log("\n");
1048 log(" -D <define>, -I <incdir>\n");
1049 log(" this options are passed as-is to the Verilog frontend for loading the\n");
1050 log(" map file. Note that the Verilog frontend is also called with the\n");
1051 log(" '-nooverwrite' option set.\n");
1052 log("\n");
1053 log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
1054 log("match cells with a type that match the text value of this attribute. Otherwise\n");
1055 log("the module name will be used to match the cell.\n");
1056 log("\n");
1057 log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
1058 log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
1059 log("\n");
1060 log("When a module in the map file has the 'techmap_maccmap' attribute set, techmap\n");
1061 log("will use 'maccmap' (see 'help maccmap') to map cells matching the module.\n");
1062 log("\n");
1063 log("When a module in the map file has the 'techmap_wrap' attribute set, techmap\n");
1064 log("will create a wrapper for the cell and then run the command string that the\n");
1065 log("attribute is set to on the wrapper module.\n");
1066 log("\n");
1067 log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
1068 log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
1069 log("the mapping module to the techmap command. At the moment the following special\n");
1070 log("wires are supported:\n");
1071 log("\n");
1072 log(" _TECHMAP_FAIL_\n");
1073 log(" When this wire is set to a non-zero constant value, techmap will not\n");
1074 log(" use this module and instead try the next module with a matching\n");
1075 log(" 'techmap_celltype' attribute.\n");
1076 log("\n");
1077 log(" When such a wire exists but does not have a constant value after all\n");
1078 log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
1079 log("\n");
1080 log(" _TECHMAP_DO_*\n");
1081 log(" This wires are evaluated in alphabetical order. The constant text value\n");
1082 log(" of this wire is a yosys command (or sequence of commands) that is run\n");
1083 log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
1084 log(" that are written using always-statements.\n");
1085 log("\n");
1086 log(" When such a wire has a non-constant value at the time it is to be\n");
1087 log(" evaluated, an error is produced. That means it is possible for such a\n");
1088 log(" wire to start out as non-constant and evaluate to a constant value\n");
1089 log(" during processing of other _TECHMAP_DO_* commands.\n");
1090 log("\n");
1091 log(" A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.\n");
1092 log(" in this case techmap will create a copy for each distinct configuration\n");
1093 log(" of constant inputs and shorted inputs at this point and import the\n");
1094 log(" constant and connected bits into the map module. All further commands\n");
1095 log(" are executed in this copy. This is a very convenient way of creating\n");
1096 log(" optimized specializations of techmap modules without using the special\n");
1097 log(" parameters described below.\n");
1098 log("\n");
1099 log(" A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.\n");
1100 log(" then techmap will recursively replace the cells in the module with their\n");
1101 log(" implementation. This is not affected by the -max_iter option.\n");
1102 log("\n");
1103 log(" It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.\n");
1104 log("\n");
1105 log(" _TECHMAP_REMOVEINIT_<port-name>_\n");
1106 log(" When this wire is set to a constant value, the init attribute of the wire(s)\n");
1107 log(" connected to this port will be consumed. This wire must have the same\n");
1108 log(" width as the given port, and for every bit that is set to 1 in the value,\n");
1109 log(" the corresponding init attribute bit will be changed to 1'bx. If all\n");
1110 log(" bits of an init attribute are left as x, it will be removed.\n");
1111 log("\n");
1112 log("In addition to this special wires, techmap also supports special parameters in\n");
1113 log("modules in the map file:\n");
1114 log("\n");
1115 log(" _TECHMAP_CELLTYPE_\n");
1116 log(" When a parameter with this name exists, it will be set to the type name\n");
1117 log(" of the cell that matches the module.\n");
1118 log("\n");
1119 log(" _TECHMAP_CONSTMSK_<port-name>_\n");
1120 log(" _TECHMAP_CONSTVAL_<port-name>_\n");
1121 log(" When this pair of parameters is available in a module for a port, then\n");
1122 log(" former has a 1-bit for each constant input bit and the latter has the\n");
1123 log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
1124 log("\n");
1125 log(" _TECHMAP_WIREINIT_<port-name>_\n");
1126 log(" When a parameter with this name exists, it will be set to the initial\n");
1127 log(" value of the wire(s) connected to the given port, as specified by the init\n");
1128 log(" attribute. If the attribute doesn't exist, x will be filled for the\n");
1129 log(" missing bits. To remove the init attribute bits used, use the\n");
1130 log(" _TECHMAP_REMOVEINIT_*_ wires.\n");
1131 log("\n");
1132 log(" _TECHMAP_BITS_CONNMAP_\n");
1133 log(" _TECHMAP_CONNMAP_<port-name>_\n");
1134 log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
1135 log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
1136 log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
1137 log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
1138 log(" This can be used to detect shorted inputs.\n");
1139 log("\n");
1140 log("When a module in the map file has a parameter where the according cell in the\n");
1141 log("design has a port, the module from the map file is only used if the port in\n");
1142 log("the design is connected to a constant value. The parameter is then set to the\n");
1143 log("constant value.\n");
1144 log("\n");
1145 log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
1146 log("and attributes of the cell that is being replaced.\n");
1147 log("\n");
1148 log("See 'help extract' for a pass that does the opposite thing.\n");
1149 log("\n");
1150 log("See 'help flatten' for a pass that does flatten the design (which is\n");
1151 log("essentially techmap but using the design itself as map library).\n");
1152 log("\n");
1153 }
1154 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1155 {
1156 log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
1157 log_push();
1158
1159 TechmapWorker worker;
1160 simplemap_get_mappers(worker.simplemap_mappers);
1161
1162 std::vector<std::string> map_files;
1163 std::string verilog_frontend = "verilog -nooverwrite -noblackbox";
1164 int max_iter = -1;
1165
1166 size_t argidx;
1167 for (argidx = 1; argidx < args.size(); argidx++) {
1168 if (args[argidx] == "-map" && argidx+1 < args.size()) {
1169 map_files.push_back(args[++argidx]);
1170 continue;
1171 }
1172 if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
1173 max_iter = atoi(args[++argidx].c_str());
1174 continue;
1175 }
1176 if (args[argidx] == "-D" && argidx+1 < args.size()) {
1177 verilog_frontend += " -D " + args[++argidx];
1178 continue;
1179 }
1180 if (args[argidx] == "-I" && argidx+1 < args.size()) {
1181 verilog_frontend += " -I " + args[++argidx];
1182 continue;
1183 }
1184 if (args[argidx] == "-assert") {
1185 worker.assert_mode = true;
1186 continue;
1187 }
1188 if (args[argidx] == "-extern") {
1189 worker.extern_mode = true;
1190 continue;
1191 }
1192 if (args[argidx] == "-recursive") {
1193 worker.recursive_mode = true;
1194 continue;
1195 }
1196 if (args[argidx] == "-autoproc") {
1197 worker.autoproc_mode = true;
1198 continue;
1199 }
1200 if (args[argidx] == "-wb") {
1201 worker.ignore_wb = true;
1202 continue;
1203 }
1204 break;
1205 }
1206 extra_args(args, argidx, design);
1207
1208 RTLIL::Design *map = new RTLIL::Design;
1209 if (map_files.empty()) {
1210 std::istringstream f(stdcells_code);
1211 Frontend::frontend_call(map, &f, "<techmap.v>", verilog_frontend);
1212 } else {
1213 for (auto &fn : map_files)
1214 if (fn.compare(0, 1, "%") == 0) {
1215 if (!saved_designs.count(fn.substr(1))) {
1216 delete map;
1217 log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
1218 }
1219 for (auto mod : saved_designs.at(fn.substr(1))->modules())
1220 if (!map->has(mod->name))
1221 map->add(mod->clone());
1222 } else {
1223 std::ifstream f;
1224 rewrite_filename(fn);
1225 f.open(fn.c_str());
1226 yosys_input_files.insert(fn);
1227 if (f.fail())
1228 log_cmd_error("Can't open map file `%s'\n", fn.c_str());
1229 Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "ilang" : verilog_frontend));
1230 }
1231 }
1232
1233 log_header(design, "Continuing TECHMAP pass.\n");
1234
1235 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1236 for (auto &it : map->modules_) {
1237 if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
1238 char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
1239 for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
1240 celltypeMap[RTLIL::escape_id(q)].insert(it.first);
1241 free(p);
1242 } else {
1243 string module_name = it.first.str();
1244 if (it.first.begins_with("\\$"))
1245 module_name = module_name.substr(1);
1246 celltypeMap[module_name].insert(it.first);
1247 }
1248 }
1249
1250 for (auto module : design->modules())
1251 worker.module_queue.insert(module);
1252
1253 while (!worker.module_queue.empty())
1254 {
1255 RTLIL::Module *module = *worker.module_queue.begin();
1256 worker.module_queue.erase(module);
1257
1258 int module_max_iter = max_iter;
1259 bool did_something = true;
1260 std::set<RTLIL::Cell*> handled_cells;
1261 while (did_something) {
1262 did_something = false;
1263 if (worker.techmap_module(design, module, map, handled_cells, celltypeMap, false))
1264 did_something = true;
1265 if (did_something)
1266 module->check();
1267 if (module_max_iter > 0 && --module_max_iter == 0)
1268 break;
1269 }
1270 }
1271
1272 log("No more expansions possible.\n");
1273 delete map;
1274
1275 log_pop();
1276 }
1277 } TechmapPass;
1278
1279 struct FlattenPass : public Pass {
1280 FlattenPass() : Pass("flatten", "flatten design") { }
1281 void help() YS_OVERRIDE
1282 {
1283 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
1284 log("\n");
1285 log(" flatten [options] [selection]\n");
1286 log("\n");
1287 log("This pass flattens the design by replacing cells by their implementation. This\n");
1288 log("pass is very similar to the 'techmap' pass. The only difference is that this\n");
1289 log("pass is using the current design as mapping library.\n");
1290 log("\n");
1291 log("Cells and/or modules with the 'keep_hierarchy' attribute set will not be\n");
1292 log("flattened by this command.\n");
1293 log("\n");
1294 log(" -wb\n");
1295 log(" Ignore the 'whitebox' attribute on cell implementations.\n");
1296 log("\n");
1297 }
1298 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
1299 {
1300 log_header(design, "Executing FLATTEN pass (flatten design).\n");
1301 log_push();
1302
1303 TechmapWorker worker;
1304 worker.flatten_mode = true;
1305
1306 size_t argidx;
1307 for (argidx = 1; argidx < args.size(); argidx++) {
1308 if (args[argidx] == "-wb") {
1309 worker.ignore_wb = true;
1310 continue;
1311 }
1312 break;
1313 }
1314 extra_args(args, argidx, design);
1315
1316
1317 std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
1318 for (auto module : design->modules())
1319 celltypeMap[module->name].insert(module->name);
1320
1321 RTLIL::Module *top_mod = NULL;
1322 if (design->full_selection())
1323 for (auto mod : design->modules())
1324 if (mod->get_bool_attribute(ID(top)))
1325 top_mod = mod;
1326
1327 std::set<RTLIL::Cell*> handled_cells;
1328 if (top_mod != NULL) {
1329 worker.flatten_do_list.insert(top_mod->name);
1330 while (!worker.flatten_do_list.empty()) {
1331 auto mod = design->module(*worker.flatten_do_list.begin());
1332 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1333 worker.flatten_done_list.insert(mod->name);
1334 worker.flatten_do_list.erase(mod->name);
1335 }
1336 } else {
1337 for (auto mod : vector<Module*>(design->modules())) {
1338 while (worker.techmap_module(design, mod, design, handled_cells, celltypeMap, false)) { }
1339 }
1340 }
1341
1342 log_suppressed();
1343 log("No more expansions possible.\n");
1344
1345 if (top_mod != NULL)
1346 {
1347 pool<RTLIL::IdString> used_modules, new_used_modules;
1348 new_used_modules.insert(top_mod->name);
1349 while (!new_used_modules.empty()) {
1350 pool<RTLIL::IdString> queue;
1351 queue.swap(new_used_modules);
1352 for (auto modname : queue)
1353 used_modules.insert(modname);
1354 for (auto modname : queue)
1355 for (auto cell : design->module(modname)->cells())
1356 if (design->module(cell->type) && !used_modules[cell->type])
1357 new_used_modules.insert(cell->type);
1358 }
1359
1360 dict<RTLIL::IdString, RTLIL::Module*> new_modules;
1361 for (auto mod : vector<Module*>(design->modules()))
1362 if (used_modules[mod->name] || mod->get_blackbox_attribute(worker.ignore_wb)) {
1363 new_modules[mod->name] = mod;
1364 } else {
1365 log("Deleting now unused module %s.\n", log_id(mod));
1366 delete mod;
1367 }
1368 design->modules_.swap(new_modules);
1369 }
1370
1371 log_pop();
1372 }
1373 } FlattenPass;
1374
1375 PRIVATE_NAMESPACE_END