passes/tests/test_autotb.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/yosys.h"
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <time.h>
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 static std::string id(std::string internal_id)
  29 {
  30         const char *str = internal_id.c_str();
  31         bool do_escape = false;
  32
  33         if (*str == '\\')
  34                 str++;
  35
  36         if ('0' <= *str && *str <= '9')
  37                 do_escape = true;
  38
  39         for (int i = 0; str[i]; i++) {
  40                 if ('0' <= str[i] && str[i] <= '9')
  41                         continue;
  42                 if ('a' <= str[i] && str[i] <= 'z')
  43                         continue;
  44                 if ('A' <= str[i] && str[i] <= 'Z')
  45                         continue;
  46                 if (str[i] == '_')
  47                         continue;
  48                 do_escape = true;
  49                 break;
  50         }
  51
  52         if (do_escape)
  53                 return "\\" + std::string(str) + " ";
  54         return std::string(str);
  55 }
  56
  57 static std::string idx(std::string str)
  58 {
  59         if (str[0] == '\\')
  60                 return str.substr(1);
  61         return str;
  62 }
  63
  64 static std::string idy(std::string str1, std::string str2 = std::string(), std::string str3 = std::string())
  65 {
  66         str1 = idx(str1);
  67         if (!str2.empty())
  68                 str1 += "_" + idx(str2);
  69         if (!str3.empty())
  70                 str1 += "_" + idx(str3);
  71         return id(str1);
  72 }
  73
  74 static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int seed)
  75 {
  76         f << stringf("`ifndef outfile\n");
  77         f << stringf("\t`define outfile \"/dev/stdout\"\n");
  78         f << stringf("`endif\n");
  79
  80         f << stringf("module testbench;\n\n");
  81
  82         f << stringf("integer i;\n");
  83         f << stringf("integer file;\n\n");
  84
  85         f << stringf("reg [31:0] xorshift128_x = 123456789;\n");
  86         f << stringf("reg [31:0] xorshift128_y = 362436069;\n");
  87         f << stringf("reg [31:0] xorshift128_z = 521288629;\n");
  88         f << stringf("reg [31:0] xorshift128_w = %u; // <-- seed value\n", seed ? seed : int(time(nullptr)));
  89         f << stringf("reg [31:0] xorshift128_t;\n\n");
  90         f << stringf("task xorshift128;\n");
  91         f << stringf("begin\n");
  92         f << stringf("\txorshift128_t = xorshift128_x ^ (xorshift128_x << 11);\n");
  93         f << stringf("\txorshift128_x = xorshift128_y;\n");
  94         f << stringf("\txorshift128_y = xorshift128_z;\n");
  95         f << stringf("\txorshift128_z = xorshift128_w;\n");
  96         f << stringf("\txorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);\n");
  97         f << stringf("end\n");
  98         f << stringf("endtask\n\n");
  99
 100         for (auto mod : design->modules())
 101         {
 102                 std::map<std::string, int> signal_in;
 103                 std::map<std::string, std::string> signal_const;
 104                 std::map<std::string, int> signal_clk;
 105                 std::map<std::string, int> signal_out;
 106
 107                 if (mod->get_bool_attribute(ID::gentb_skip))
 108                         continue;
 109
 110                 int count_ports = 0;
 111                 log("Generating test bench for module `%s'.\n", mod->name.c_str());
 112                 for (auto wire : mod->wires()) {
 113                         if (wire->port_output) {
 114                                 count_ports++;
 115                                 signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
 116                                 f << stringf("wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
 117                         } else if (wire->port_input) {
 118                                 count_ports++;
 119                                 bool is_clksignal = wire->get_bool_attribute(ID::gentb_clock);
 120                                 for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); ++it3)
 121                                 for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); ++it4) {
 122                                         if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
 123                                                 continue;
 124                                         RTLIL::SigSpec &signal = (*it4)->signal;
 125                                         for (auto &c : signal.chunks())
 126                                                 if (c.wire == wire)
 127                                                         is_clksignal = true;
 128                                 }
 129                                 if (is_clksignal && wire->attributes.count(ID::gentb_constant) == 0) {
 130                                         signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
 131                                 } else {
 132                                         signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
 133                                         if (wire->attributes.count(ID::gentb_constant) != 0)
 134                                                 signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes[ID::gentb_constant].as_string();
 135                                 }
 136                                 f << stringf("reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
 137                         }
 138                 }
 139                 f << stringf("%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
 140                 for (auto wire : mod->wires()) {
 141                         if (wire->port_output || wire->port_input)
 142                                 f << stringf("\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
 143                                                 idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : "");
 144                 }
 145                 f << stringf(");\n\n");
 146
 147                 f << stringf("task %s;\n", idy(mod->name.str(), "reset").c_str());
 148                 f << stringf("begin\n");
 149                 int delay_counter = 0;
 150                 for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
 151                         f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
 152                 for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it)
 153                         f << stringf("\t%s <= #%d 0;\n", it->first.c_str(), ++delay_counter*2);
 154                 f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
 155                 for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
 156                         f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
 157                         f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
 158                 }
 159                 delay_counter = 0;
 160                 for (auto it = signal_in.begin(); it != signal_in.end(); ++it)
 161                         f << stringf("\t%s <= #%d ~0;\n", it->first.c_str(), ++delay_counter*2);
 162                 f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
 163                 for (auto it = signal_clk.begin(); it != signal_clk.end(); ++it) {
 164                         f << stringf("\t#100; %s <= 1;\n", it->first.c_str());
 165                         f << stringf("\t#100; %s <= 0;\n", it->first.c_str());
 166                 }
 167                 delay_counter = 0;
 168                 for (auto it = signal_in.begin(); it != signal_in.end(); ++it) {
 169                         if (signal_const.count(it->first) == 0)
 170                                 continue;
 171                         f << stringf("\t%s <= #%d 'b%s;\n", it->first.c_str(), ++delay_counter*2, signal_const[it->first].c_str());
 172                 }
 173                 f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
 174                 f << stringf("end\n");
 175                 f << stringf("endtask\n\n");
 176
 177                 f << stringf("task %s;\n", idy(mod->name.str(), "update_data").c_str());
 178                 f << stringf("begin\n");
 179                 delay_counter = 0;
 180                 for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
 181                         if (signal_const.count(it->first) > 0)
 182                                 continue;
 183                         f << stringf("\txorshift128;\n");
 184                         f << stringf("\t%s <= #%d { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };\n", it->first.c_str(), ++delay_counter*2);
 185                 }
 186                 f << stringf("\t#%d;\n", ((2*delay_counter+99)/100)*100);
 187                 f << stringf("end\n");
 188                 f << stringf("endtask\n\n");
 189
 190                 f << stringf("task %s;\n", idy(mod->name.str(), "update_clock").c_str());
 191                 f << stringf("begin\n");
 192                 if (signal_clk.size()) {
 193                         f << stringf("\txorshift128;\n");
 194                         f << stringf("\t{");
 195                         int total_clock_bits = 0;
 196                         for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
 197                                 f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
 198                                 total_clock_bits += it->second;
 199                         }
 200                         f << stringf(" } = {");
 201                         for (auto it = signal_clk.begin(); it != signal_clk.end(); it++)
 202                                 f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
 203                         f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits + 1);
 204                 }
 205                 f << stringf("end\n");
 206                 f << stringf("endtask\n\n");
 207
 208                 char shorthand = 'A';
 209                 std::vector<std::string> header1;
 210                 std::string header2 = "";
 211
 212                 f << stringf("task %s;\n", idy(mod->name.str(), "print_status").c_str());
 213                 f << stringf("begin\n");
 214                 f << stringf("\t$fdisplay(file, \"#OUT# %%b %%b %%b %%t %%d\", {");
 215                 if (signal_in.size())
 216                         for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
 217                                 f << stringf("%s %s", it == signal_in.begin() ? "" : ",", it->first.c_str());
 218                                 int len = it->second;
 219                                 header2 += ", \"";
 220                                 if (len > 1)
 221                                         header2 += "/", len--;
 222                                 while (len > 1)
 223                                         header2 += "-", len--;
 224                                 if (len > 0)
 225                                         header2 += shorthand, len--;
 226                                 header2 += "\"";
 227                                 header1.push_back("    " + it->first);
 228                                 header1.back()[0] = shorthand;
 229                                 shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
 230                         }
 231                 else {
 232                         f << stringf(" 1'bx");
 233                         header2 += ", \"#\"";
 234                 }
 235                 f << stringf(" }, {");
 236                 header2 += ", \" \"";
 237                 if (signal_clk.size()) {
 238                         for (auto it = signal_clk.begin(); it != signal_clk.end(); it++) {
 239                                 f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
 240                                 int len = it->second;
 241                                 header2 += ", \"";
 242                                 if (len > 1)
 243                                         header2 += "/", len--;
 244                                 while (len > 1)
 245                                         header2 += "-", len--;
 246                                 if (len > 0)
 247                                         header2 += shorthand, len--;
 248                                 header2 += "\"";
 249                                 header1.push_back("    " + it->first);
 250                                 header1.back()[0] = shorthand;
 251                                 shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
 252                         }
 253                 } else {
 254                         f << stringf(" 1'bx");
 255                         header2 += ", \"#\"";
 256                 }
 257                 f << stringf(" }, {");
 258                 header2 += ", \" \"";
 259                 if (signal_out.size()) {
 260                         for (auto it = signal_out.begin(); it != signal_out.end(); it++) {
 261                                 f << stringf("%s %s", it == signal_out.begin() ? "" : ",", it->first.c_str());
 262                                 int len = it->second;
 263                                 header2 += ", \"";
 264                                 if (len > 1)
 265                                         header2 += "/", len--;
 266                                 while (len > 1)
 267                                         header2 += "-", len--;
 268                                 if (len > 0)
 269                                         header2 += shorthand, len--;
 270                                 header2 += "\"";
 271                                 header1.push_back("    " + it->first);
 272                                 header1.back()[0] = shorthand;
 273                                 shorthand = shorthand == 'Z' ? 'A' : shorthand+1;
 274                         }
 275                 } else {
 276                         f << stringf(" 1'bx");
 277                         header2 += ", \"#\"";
 278                 }
 279                 f << stringf(" }, $time, i);\n");
 280                 f << stringf("end\n");
 281                 f << stringf("endtask\n\n");
 282
 283                 f << stringf("task %s;\n", idy(mod->name.str(), "print_header").c_str());
 284                 f << stringf("begin\n");
 285                 f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
 286                 for (auto &hdr : header1)
 287                         f << stringf("\t$fdisplay(file, \"#OUT#   %s\");\n", hdr.c_str());
 288                 f << stringf("\t$fdisplay(file, \"#OUT#\");\n");
 289                 f << stringf("\t$fdisplay(file, {\"#OUT# \"%s});\n", header2.c_str());
 290                 f << stringf("end\n");
 291                 f << stringf("endtask\n\n");
 292
 293                 f << stringf("task %s;\n", idy(mod->name.str(), "test").c_str());
 294                 f << stringf("begin\n");
 295                 f << stringf("\t$fdisplay(file, \"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
 296                 f << stringf("\t%s;\n", idy(mod->name.str(), "reset").c_str());
 297                 f << stringf("\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
 298                 f << stringf("\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
 299                 f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
 300                 f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
 301                 f << stringf("\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
 302                 f << stringf("\tend\n");
 303                 f << stringf("end\n");
 304                 f << stringf("endtask\n\n");
 305         }
 306
 307         f << stringf("initial begin\n");
 308         f << stringf("\t// $dumpfile(\"testbench.vcd\");\n");
 309         f << stringf("\t// $dumpvars(0, testbench);\n");
 310         f << stringf("\tfile = $fopen(`outfile);\n");
 311         for (auto module : design->modules())
 312                 if (!module->get_bool_attribute(ID::gentb_skip))
 313                         f << stringf("\t%s;\n", idy(module->name.str(), "test").c_str());
 314         f << stringf("\t$fclose(file);\n");
 315         f << stringf("\t$finish;\n");
 316         f << stringf("end\n\n");
 317
 318         f << stringf("endmodule\n");
 319 }
 320
 321 struct TestAutotbBackend : public Backend {
 322         TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { }
 323         void help() YS_OVERRIDE
 324         {
 325                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 326                 log("\n");
 327                 log("    test_autotb [options] [filename]\n");
 328                 log("\n");
 329                 log("Automatically create primitive Verilog test benches for all modules in the\n");
 330                 log("design. The generated testbenches toggle the input pins of the module in\n");
 331                 log("a semi-random manner and dumps the resulting output signals.\n");
 332                 log("\n");
 333                 log("This can be used to check the synthesis results for simple circuits by\n");
 334                 log("comparing the testbench output for the input files and the synthesis results.\n");
 335                 log("\n");
 336                 log("The backend automatically detects clock signals. Additionally a signal can\n");
 337                 log("be forced to be interpreted as clock signal by setting the attribute\n");
 338                 log("'gentb_clock' on the signal.\n");
 339                 log("\n");
 340                 log("The attribute 'gentb_constant' can be used to force a signal to a constant\n");
 341                 log("value after initialization. This can e.g. be used to force a reset signal\n");
 342                 log("low in order to explore more inner states in a state machine.\n");
 343                 log("\n");
 344                 log("The attribute 'gentb_skip' can be attached to modules to suppress testbench\n");
 345                 log("generation.\n");
 346                 log("\n");
 347                 log("    -n <int>\n");
 348                 log("        number of iterations the test bench should run (default = 1000)\n");
 349                 log("\n");
 350                 log("    -seed <int>\n");
 351                 log("        seed used for pseudo-random number generation (default = 0).\n");
 352                 log("        a value of 0 will cause an arbitrary seed to be chosen, based on\n");
 353                 log("        the current system time.\n");
 354                 log("\n");
 355         }
 356         void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 357         {
 358                 int num_iter = 1000;
 359                 int seed = 0;
 360
 361                 log_header(design, "Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n");
 362
 363                 int argidx;
 364                 for (argidx = 1; argidx < GetSize(args); argidx++)
 365                 {
 366                         if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
 367                                 num_iter = atoi(args[++argidx].c_str());
 368                                 continue;
 369                         }
 370                         if (args[argidx] == "-seed" && argidx+1 < GetSize(args)) {
 371                                 seed = atoi(args[++argidx].c_str());
 372                                 continue;
 373                         }
 374                         break;
 375                 }
 376
 377                 extra_args(f, filename, args, argidx);
 378                 autotest(*f, design, num_iter, seed);
 379         }
 380 } TestAutotbBackend;
 381
 382 PRIVATE_NAMESPACE_END
 383