pifixedload.mdwn

   1 <!-- This defines DRAFT instructions that are to be proposed for SV -->
   2
   3 <!-- This defines instructions that load from RAM to a register -->
   4 <!-- Effective Address is always RA, and the usual EA is stored late in RA -->
   5
   6 <!-- Note that these pages also define equivalent store instructions, -->
   7 <!-- these are described in pifixedstore.mdwn -->
   8
   9
  10
  11 # Load Byte and Zero with Post-Update
  12
  13 D-Form
  14
  15 * lbzup RT,D(RA)
  16
  17 Pseudo-code:
  18
  19     EA <- (RA)
  20     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  21     RA <- (RA) + EXTS(D)
  22
  23 Description:
  24
  25     Let the effective address (EA) be register RA. The
  26     byte in storage addressed by EA is loaded into RT[56:63].
  27     RT[0:55] are set to 0.
  28
  29     The sum (RA) + D is placed into register RA.
  30
  31     If RA=0 or RA=RT, the instruction form is invalid.
  32
  33 Special Registers Altered:
  34
  35     None
  36
  37 # Load Byte and Zero with Post-Update Indexed
  38
  39 X-Form
  40
  41 * lbzupx RT,RA,RB
  42
  43 Pseudo-code:
  44
  45     EA <- (RA)
  46     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
  47     RA <- (RA) + (RB)
  48
  49 Description:
  50
  51     Let the effective address (EA) be register RA.
  52     The byte in storage addressed by EA is loaded into
  53     RT[56:63]. RT[0:55] are set to 0.
  54
  55     The sum (RA) + (RB) is placed into register RA.
  56
  57     If RA=0 or RA=RT, the instruction form is invalid.
  58
  59 Special Registers Altered:
  60
  61     None
  62
  63 # Load Halfword and Zero with Post-Update
  64
  65 D-Form
  66
  67 * lhzup RT,D(RA)
  68
  69 Pseudo-code:
  70
  71     EA <- (RA)
  72     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  73     RA <- (RA) + EXTS(D)
  74
  75 Special Registers Altered:
  76
  77     None
  78
  79 # Load Halfword and Zero with Post-Update Indexed
  80
  81 X-Form
  82
  83 * lhzupx RT,RA,RB
  84
  85 Pseudo-code:
  86
  87     EA <- (RA)
  88     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
  89     RA <- (RA) + (RB)
  90
  91 Special Registers Altered:
  92
  93     None
  94
  95 # Load Halfword Algebraic with Post-Update
  96
  97 D-Form
  98
  99 * lhaup RT,D(RA)
 100
 101 Pseudo-code:
 102
 103     EA <- (RA)
 104     RT <- EXTS(MEM(EA, 2))
 105     RA <- (RA) + EXTS(D)
 106
 107 Special Registers Altered:
 108
 109     None
 110
 111 # Load Halfword Algebraic with Post-Update Indexed
 112
 113 X-Form
 114
 115 * lhaupx RT,RA,RB
 116
 117 Pseudo-code:
 118
 119     EA <- (RA)
 120     RT <- EXTS(MEM(EA, 2))
 121     RA <- (RA) + (RB)
 122
 123 Special Registers Altered:
 124
 125     None
 126
 127 # Load Word and Zero with Post-Update
 128
 129 D-Form
 130
 131 * lwzup RT,D(RA)
 132
 133 Pseudo-code:
 134
 135     EA <- (RA)
 136     RT <- [0]*32 || MEM(EA, 4)
 137     RA <- (RA) + EXTS(D)
 138
 139 Special Registers Altered:
 140
 141     None
 142
 143 # Load Word and Zero with Post-Update Indexed
 144
 145 X-Form
 146
 147 * lwzupx RT,RA,RB
 148
 149 Pseudo-code:
 150
 151     EA <- (RA)
 152     RT <- [0] * 32 || MEM(EA, 4)
 153     RA <- (RA) + (RB)
 154
 155 Special Registers Altered:
 156
 157     None
 158
 159 # Load Word Algebraic with Post-Update Indexed
 160
 161 X-Form
 162
 163 * lwaupx RT,RA,RB
 164
 165 Pseudo-code:
 166
 167     EA <- (RA)
 168     RT <- EXTS(MEM(EA, 4))
 169     RA <- (RA) + (RB)
 170
 171 Special Registers Altered:
 172
 173     None
 174
 175 # Load Doubleword with Post-Update Indexed
 176
 177 DS-Form
 178
 179 * ldup RT,DS(RA)
 180
 181 Pseudo-code:
 182
 183     EA <- (RA)
 184     RT <- MEM(EA, 8)
 185     RA <- (RA) + EXTS(DS || 0b00)
 186
 187 Special Registers Altered:
 188
 189     None
 190
 191 # Load Doubleword with Post-Update Indexed
 192
 193 X-Form
 194
 195 * ldupx RT,RA,RB
 196
 197 Pseudo-code:
 198
 199     EA <- (RA)
 200     RT <- MEM(EA, 8)
 201     RA <- (RA) + (RB)
 202
 203 Special Registers Altered:
 204
 205     None
 206