1 \documentclass[slidestop
]{beamer
}
2 \usepackage{beamerthemesplit
}
6 \title{Pin Multiplexer
}
8 \author{Luke Kenneth Casson Leighton
}
15 \huge{Pin Multiplexer
}\\
17 \Large{Auto-generating documentation, code \\
18 and resources for a Pinmux
}\\
20 \Large{Saving time and money for SoC / EC designers\\
21 in the RISC-V Ecosystem and beyond
}\\
23 \Large{[proposed for
] Chennai
9th RISC-V Workshop
}\\
30 \frame{\frametitle{Credits and Acknowledgements
}
33 \item TODO
\vspace{10pt
}
38 \frame{\frametitle{Glossary
}
41 \item GPIO: general-purpose reconfigureable I/O (Input/Output).
42 \item Pin: an I/O pad. May be driven (input) or may drive (output).
43 \item FN: term for a single-wire "function", such as UART
\_TX,
44 I2C
\_SDA, SDMMC
\_D0 etc. may be an input, output or both
45 (bi-directional case: two wires are
{\it always
} allocated, one
46 for input to the function and one for output from the function).
47 \item Bus: a group of bi-directional functions (SDMMC D0 to D3)
48 where the direction is ganged and
{\it under the Bus's control
}
49 \item Input Priority Muxer: a multiplexer with N selector
50 wires and N associated inputs. The lowest (highest?) indexed
51 "selector" enabled results in its
52 input being routed to the output.
53 \item Output Muxer: a many-to-one "redirector" where any one
54 input is "routed" to the output, based on a selector "address".
59 \frame{\frametitle{Why, How and What is a Pinmux?
}
62 \item Why? To save cost, increase yield, and to target multiple
63 markets with the same design, thereby increasing uptake
64 and consequently taking advantage of volume pricing.
\vspace{4pt
}
66 Summary: it's all about making more money!
\vspace{4pt
}
67 \item How? By multiplexing many more functions (
100 to
1,
200) than there
68 are actual available pins (
48 to
500), the required chip package
69 is far less costly and the chip more desirable
\vspace{4pt
}
70 \item What? A many-to-many dynamically-configureable router of
71 I/O functions to I/O pins
\vspace{4pt
}
72 \item \bf{Note: actual muxing is deceptively simple, but like
73 a DRAM cell it's actually about the ancillaries / extras
}
78 \frame{\frametitle{What options are available (at time of writing)?
[1]}
81 {\bf Commercial licensed
}:
85 \item Flexibility: unknown.
86 \item Language: unknown.
87 \item Capability for auto-generation of Docs: unknown.
88 \item Capability for auto-generation of ancillary resources: unknown.
89 \item Suitability for wide range of systems: unknown.
91 \item Suitability for saving RISC-V ecosystem money:
{\bf NONE
}
92 \item Suitability for collaboration:
{\bf ZERO
} (i.e. don't bother)
95 Commercial licensees are isolated and cut off from the benefits
96 and resources of the Libre world. Translation: USD \$
200k+ NREs.
100 \frame{\frametitle{What options are available (at time of writing)?
[2]}
103 {\bf SiFive IOF (Freedom E310, Unleashed U540)
}:
107 \item Flexibility: not so good.
108 \item Language: chisel3.
109 \item Capability for auto-generation of Docs: none.
110 \item Capability for auto-generation of ancillary resources: partial.
111 \item Suitability for wide range of systems: not so good.
113 \item Suitability for saving RISC-V ecosystem money:
{\bf Low
}\\
114 \item Suitability for collaboration:
{\bf GOOD
} (but: written in Chisel3)
117 Using SiFive IOF has Libre benefits, but it's incomplete and
118 harder to find Chisel3 programmers (than e.g. for python).
122 \frame{\frametitle{What options are available (at time of writing)?
[3]}
127 None. No suitable
\vspace{20pt
}\\
128 Libre-licensed
\vspace{20pt
}\\
129 pinmux exists
\vspace{20pt
}
132 (which is really weird, given how there's so many libre UART,
133 SPI and other peripheral libraries, even libre-licensed PCIe and
134 SATA PHYs and even USB3 Pipe, hence the reason for this initiative)
140 \frame{\frametitle{Associated Extras
}
143 \item Design Specification (what markets to target)
144 \item Scenario analysis (
{\bf whether
} the chip will fit "markets")
145 \item Documentation: Summary sheet, Technical Reference Manual.
147 \item Control Interface (AXI4 / Wishbone / TileLink / other)
149 \item Linux kernel drivers, DTB, libopencm3, Arduino libraries etc.
153 \item Shakti M-Class has
160 pins with a
99.5\% full
4-way mux
154 \item Almost
640-way routing,
6 "scenarios" (
7th TBD),
155 100+ page Manual needed,
156 \bf{17,
500 lines of auto-generated code
}
165 ALL of these
\vspace{20pt
}\\
166 can be
\vspace{20pt
}\\
167 auto-generated
\vspace{30pt
}
170 (from the Design Specification, after Scenario Analysis)
176 \frame{\frametitle{Example:
7 banks,
4-way mux,
160 pins
}
178 \includegraphics[height=
1.5in
]{example_pinmux.jpg
}\\
179 7 "banks" with separate VCC. Each no more than
32 bits
182 \item { \bf 17,
500 lines of auto-generated HDL (and climbing)
}
183 \item { \bf 12,
500 lines of auto-generated Summary/Analysis
}
184 \item Technical Reference Manual expected to be
100+ pages
189 \frame{\frametitle{Reduce workload, reduce duplication, reduce risk and cost
}
192 \item Auto-generate everything: documentation, code, libraries etc.
194 \item Standardise: similar to PLIC, propose GPIO and Pinmux\\
195 saves engineering effort, design effort and much more
197 \item Standardise format of configuration registers:
198 saves code duplication effort (multiple software environments)
200 \item Add support for multiple code formats: Chisel3 (SiFive IOF),
201 BSV (Bluespec), Verilog, VHDL, MyHDL.
203 \item Multiple auto-generated code-formats permits cross-validation:\\
204 auto-generated test suite in one HDL can validate a muxer
205 generated for a different target HDL.
211 \frame{\frametitle{Design Spec and Scenario Analysis
}
214 \item Analyse the target markets (scenarios) that the chip will sell in\\
215 (multiple markets increases sales volume, reduces chip cost)
217 \item Scenarios represent target markets: ICs to be connected\\
218 (GPS, NAND IC, WIFI etc. May require prototype schematics
219 drawn up, or client-supplied schematics analysed).
221 \item Create a formal (python-based) specification for the pinmux
223 \item Add scenarios (in python), check that they meet requirements\\
224 { \bf (before spending money on hardware engineers!)
}
226 \item Analyse the scenarios: if pins are missing, alter and repeat.\\
228 \item Eventually the pinmux meets all requirements...\\
229 { \bf without spending USD \$
5-
50m to find out it doesn't!
}
235 \frame{\frametitle{Muxer cases to handle (One/Many to One/Many) etc.
}
238 \item One FN outputs to Many Pins: no problem\\
239 (weird configuration by end-user, but no damage to ASIC)
240 \item One Pin to Many FN inputs: no problem\\
241 (weird configuration by end-user, but no damage to ASIC)
242 \item Many Pins to One FN input:
{\bf Priority Mux needed
}\\
243 No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged
244 \item Many FN outputs simultaneously to one Pin:
{\bf does not occur
}\\
245 (not desirable and not possible, as part of the pinmux design)
246 \item Some FNs (I2C
\_SDA, SD
\_D0.
.3) are I/O Buses\\
247 Bi-directional control of the Pin must be handed to the
249 \item Nice to have: Bus sets pintype, signal strength etc.\\
250 e.g. selecting SD/MMC doesn't need manual pin-config.\\
251 \bf{caveat: get that wrong and the ASIC can't be sold
}
256 \frame{\frametitle{Pin Configuration, input and output
}
258 In/out:
{\bf Note: these all require multiplexing
}
260 \item Output-Enable (aka Input disable): switches pad to In or Out
261 \item Output (actually an input wire controlling pin's level, HI/LO)
262 \item Input (actually an output wire set based on pin's driven level)
264 Characteristics:
{\bf Note: these do not require multiplexing
}
266 \item Output current level:
10mA /
20mA /
30mA /
40mA
267 \item Input hysteresis: low / middle / high. Stops signal noise
268 \item Pin characteristics: CMOS Push-Push / Open-Drain
269 \item Pull-up enable: built-in
10k (
50k?) resistor
270 \item Pull-down enable: built-in
10k (
50k?) resistor
271 \item Muxing and IRQ Edge-detection not part of the I/O pin
272 \item Other? (impedance? not normally part of commercial pinmux)
277 \frame{\frametitle{Standard GPIO
4-way in/out Mux and I/O pad
}
279 \includegraphics[height=
2.5in
]{../shakti/m_class/mygpiomux.jpg
}\\
280 {\bf 4-in,
4-out, pullup/down, hysteresis, edge-detection (EINT)
}
284 \frame{\frametitle{Separating Pin Configuration, input and output
}
287 \item Standard Mux design
{\bf cannot deal with many-to-one inputs
}\\
288 (SiFive IOF source code from Freedom U310 cannot, either)
290 \item I/O pad configuration conflated with In-Muxer conflated with
291 Out-Muxer conflated with GPIO conflated with EINT.
294 {\bf IMPORTANT to separate all of these out:
297 \item EINTs to be totally separate FNs. managed by RISC-V PLIC\\
298 (If every GPIO was an EINT it would mean
100+ IRQs)
300 \item GPIO In/Out/Direction treated just like any other FN\\
301 (but happen to have AXI4 - or other - memory-mapping)
303 \item Pad configuration separated and given one-to-one Registers\\
304 (SRAMs set by AXI4 to control mux, pullup, current etc.)
308 \frame{\frametitle{Register-to-pad "control" settings
}
310 \includegraphics[height=
2.5in
]{reg_gpio_cap_ctrl.jpg
}\\
311 {\bf pullup/down, hysteresis, current, edge-detection
}
316 \frame{\frametitle{GPIO (only): Simplified I/O pad Diagram (FN only)
}
318 \includegraphics[height=
2.5in
]{reg_gpio_pinblock.jpg
}\\
319 {\bf 3 wires: IN, OUT, OUTEN (also = !INEN)
}
324 \frame{\frametitle{Output Muxer (very simple)
}
326 \includegraphics[height=
1.1in
]{reg_gpio_out_mux.jpg
}\\
327 {\bf Ouput Muxer using
2-bit address selection
}\\
330 \item Very straightforward (deceptively so, like SRAM cells)
331 \item Used in both OUT routing and Direction-control routing\\
332 (same address for each, connected to same FNs)
333 \item More complex pinmux will have
3-bit addressing (
8 FNs)\\
334 (Note: not all outputs will be connected, depends on pinmux)
339 \frame{\frametitle{In/Out muxing, direction control: GPIO just a FN
}
341 \includegraphics[height=
2.5in
]{reg_gpio_fn_ctrl.jpg
}\\
342 {\bf Note: function can control I/O direction (bus)
}
347 \frame{\frametitle{Direction Control: Function not bi-directional (bus)
}
349 \includegraphics[height=
2.5in
]{reg_gpio_fn_ctrl2.jpg
}\\
350 Note: Function
{\bf does not
} control I/O direction
355 \frame{\frametitle{Output (and OUTEN) Wiring.
2 pins,
2 GPIO,
2 Fns
}
357 \includegraphics[height=
2.5in
]{reg_gpio_out_wiring.jpg
}\\
358 {\bf Reg0 for Pin0, Reg1 for Pin1, Output and OUTEN same mux
}
363 \frame{\frametitle{Input Selection and Priority Muxing
}
365 \includegraphics[height=
0.75in
]{reg_gpio_comparator.jpg
}\\
366 {\bf Muxer enables input selection
}\\
368 \includegraphics[height=
1.25in
]{reg_gpio_in_prioritymux.jpg
}\\
369 {\bf However multiple inputs must be prioritised
}
374 \frame{\frametitle{Input Priority-Mux Wiring: very different from Out-Mux
}
376 \includegraphics[height=
2.5in
]{reg_gpio_in_wiring.jpg
}\\
377 {\bf Pin Mux selection vals NOT same as FN selection vals
}
382 \frame{\frametitle{Input Priority-Mux Wiring
}
385 \item In-Muxer selection number (
0,
1,
2,
3) obviously has to match
386 with Out-Muxer order (otherwise a bi-directional FN
387 needs different Mux-register settings for
388 selecting either IN or OUT)
390 \item Priority-mux selection values do not actually matter,
391 and have nothing to do with the actual Muxer settings.
393 \item GPIO FN's input muxer is nothing more than an AND gate\\
394 (you never route more than one pin to one GPIO)
396 \item Any other FN with only
1:
1 on its IN also just an AND gate \\
397 (this just always happens to be true for GPIO)
399 \item Not all FNs have input capability: clearly they will not
400 be included in the In-Muxing.
405 \frame{\frametitle{Summary
}
408 \item Value of Libre/Open pimux dramatically underestimated\\
409 (and does not presently exist: SiFive's IOF not suitable as-is)\\
410 {\bf Only current option: license a commercial Pinmux
}
411 \item Actual muxing (like SRAM cells) is deceptively simple
412 \item Actual pinmuxes are enormous: auto-generation essential
413 \item HDLs completely unsuited to auto-generation task\\
414 (TRM, docs):
{\bf Modern OO language needed i.e. python
}
415 \item Scenario Analysis / Verification and auto-generation of
416 different HDLs far easier in a Modern OO language\\
417 (better libraries, more developers)
418 \item Standardisation for RISC-V saves implementors from huge
419 duplication cost (HDL, firmware, docs, maintenance)
420 \item { \bf Ultimately it's about saving money and reducing risk
}
427 {\Huge The end
\vspace{20pt
}\\
428 Thank you
\vspace{20pt
}\\
429 Questions?
\vspace{20pt
}
434 \item http://libre-riscv.org/shakti/m
\_class/pinmux/