2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
15 acc : in std_ulogic_vector(BITS-1 downto 0);
16 acc_en : in std_ulogic;
17 lru : out std_ulogic_vector(BITS-1 downto 0)
21 architecture rtl of plru is
22 constant count : positive := 2 ** BITS - 1;
23 subtype node_t is integer range 0 to count;
24 type tree_t is array(node_t) of std_ulogic;
29 -- XXX Check if we can turn that into a little ROM instead that
30 -- takes the tree bit vector and returns the LRU. See if it's better
31 -- in term of FPGA resouces usage...
32 get_lru: process(tree)
33 variable node : node_t;
36 for i in 0 to BITS-1 loop
37 -- report "GET: i:" & integer'image(i) & " node:" & integer'image(node) & " val:" & std_ulogic'image(tree(node));
38 lru(BITS-1-i) <= tree(node);
41 if tree(node) = '1' then
50 update_lru: process(clk)
51 variable node : node_t;
52 variable abit : std_ulogic;
54 if rising_edge(clk) then
56 tree <= (others => '0');
57 elsif acc_en = '1' then
59 for i in 0 to BITS-1 loop
60 abit := acc(BITS-1-i);
61 tree(node) <= not abit;
62 -- report "UPD: i:" & integer'image(i) & " node:" & integer'image(node) & " val" & std_ulogic'image(not abit);