2 use ieee.std_logic_1164.all;
6 use work.wishbone_types.all;
11 architecture behave of plru_tb is
12 signal clk : std_ulogic;
13 signal rst : std_ulogic;
15 constant clk_period : time := 10 ns;
17 signal acc_en : std_ulogic;
18 signal acc : std_ulogic_vector(2 downto 0);
19 signal lru : std_ulogic_vector(2 downto 0);
22 plru0: entity work.plru
38 wait for clk_period/2;
40 wait for clk_period/2;
46 wait for 2*clk_period;
53 wait for 4*clk_period;
55 report "accessing 1:";
59 report "lru:" & to_hstring(lru);
61 report "accessing 2:";
64 report "lru:" & to_hstring(lru);
66 report "accessing 7:";
69 report "lru:" & to_hstring(lru);
71 report "accessing 4:";
74 report "lru:" & to_hstring(lru);
76 report "accessing 3:";
79 report "lru:" & to_hstring(lru);
81 report "accessing 5:";
84 report "lru:" & to_hstring(lru);
86 report "accessing 3:";
89 report "lru:" & to_hstring(lru);
91 report "accessing 5:";
94 report "lru:" & to_hstring(lru);
96 report "accessing 6:";
99 report "lru:" & to_hstring(lru);
101 report "accessing 0:";
104 report "lru:" & to_hstring(lru);