Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
[gem5.git] / python / m5 / objects / BaseCPU.mpy
1 simobj BaseCPU(SimObject):
2 type = 'BaseCPU'
3 abstract = True
4 icache = Param.BaseMem(NULL, "L1 instruction cache object")
5 dcache = Param.BaseMem(NULL, "L1 data cache object")
6
7 if build_env['FULL_SYSTEM']:
8 dtb = Param.AlphaDTB("Data TLB")
9 itb = Param.AlphaITB("Instruction TLB")
10 mem = Param.FunctionalMemory("memory")
11 system = Param.BaseSystem(parent.any, "system object")
12 else:
13 workload = VectorParam.Process("processes to run")
14
15 max_insts_all_threads = Param.Counter(0,
16 "terminate when all threads have reached this inst count")
17 max_insts_any_thread = Param.Counter(0,
18 "terminate when any thread reaches this inst count")
19 max_loads_all_threads = Param.Counter(0,
20 "terminate when all threads have reached this load count")
21 max_loads_any_thread = Param.Counter(0,
22 "terminate when any thread reaches this load count")
23
24 defer_registration = Param.Bool(False,
25 "defer registration with system (for sampling)")