Merge zizzer:/bk/m5 into zeep.eecs.umich.edu:/z/saidi/work/m5-clean
[gem5.git] / python / m5 / objects / BaseCPU.py
1 from m5 import *
2 class BaseCPU(SimObject):
3 type = 'BaseCPU'
4 abstract = True
5 icache = Param.BaseMem(NULL, "L1 instruction cache object")
6 dcache = Param.BaseMem(NULL, "L1 data cache object")
7
8 if build_env['FULL_SYSTEM']:
9 dtb = Param.AlphaDTB("Data TLB")
10 itb = Param.AlphaITB("Instruction TLB")
11 mem = Param.FunctionalMemory("memory")
12 system = Param.System(Parent.any, "system object")
13 else:
14 workload = VectorParam.Process("processes to run")
15
16 max_insts_all_threads = Param.Counter(0,
17 "terminate when all threads have reached this inst count")
18 max_insts_any_thread = Param.Counter(0,
19 "terminate when any thread reaches this inst count")
20 max_loads_all_threads = Param.Counter(0,
21 "terminate when all threads have reached this load count")
22 max_loads_any_thread = Param.Counter(0,
23 "terminate when any thread reaches this load count")
24
25 defer_registration = Param.Bool(False,
26 "defer registration with system (for sampling)")
27
28 clock = Param.Clock(Parent.clock, "clock speed")