1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 # RISC-V Instruction Set Architecture
26 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
29 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
30 of the project implies, we will be following the RISC-V ISA I due to it
31 being open-source and also because of the huge software and hardware
32 ecosystem building around it. There are other open-source ISAs but none
33 of them have the same momentum and energy behind it as RISC-V.
35 To fully take advantage of the RISC-V ecosystem, it is important to be
36 compliant with the RISC-V standards. Doing so will allow us to to reuse
37 most software as-is and avoid major forks.
39 * [Official compiled PDFs of RISC-V ISA Manual]
40 (https://github.com/riscv/riscv-isa-manual/releases/latest)
41 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
42 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
43 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
45 Note: As far as I know, we aren't using the RISC-V V Extension directly
46 at the moment. However, there are many wiki pages that make a reference
47 to the V extension so it would be good to include it here as a reference
48 for comparative/informative purposes with regard to Simple-V.
51 # RTL Arithmetic SQRT, FPU etc.
54 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
55 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
57 ## CORDIC and related algorithms
58 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
59 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
60 - Does not have an easy way of computing tan(x)
61 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
62 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
64 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
66 Almost all modern computers follow the IEEE Floating-Point Standard. Of
67 course, we will follow it as well for interoperability.
69 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
71 Note: Even though this is such an important standard used by everyone,
72 it is unfortunately not freely available and requires a payment to
73 access. However, each of the Libre RISC-V members already have access
76 ## Past FPU Mistakes to learn from
78 * [Intel Underestimates Error Bounds by 1.3 quintillion on
79 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
80 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
84 The Khronos Group creates open standards for authoring and acceleration
85 of graphics, media, and computation. It is a requirement for our hybrid
86 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
87 in order to be commercially-competitive in both areas: especially Vulkan
88 and OpenCL being the most important. SPIR-V is also important for the
91 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
92 switching between different accuracy levels, in userspace applications.
94 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
96 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
97 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
98 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
100 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
102 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
104 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
106 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
107 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
108 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
110 Note: We are implementing hardware accelerated Vulkan and
111 OpenCL while relying on other software projects to translate APIs to
112 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
114 # Graphics and Compute API Stack
116 I found this informative post that mentions Kazan and a whole bunch of
117 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
118 although performance is not evaluated.
120 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
122 # Various POWER Communities
123 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
124 The T2080 is a POWER8 chip.
125 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
126 Supporting/Raising awareness of various POWER related open projects on the FOSS
128 - [OpenPOWER](https://openpowerfoundation.org)
129 Promotes and ensure compliance with the Power ISA amongst members.
130 - [OpenCapi](https://opencapi.org)
131 High performance interconnect for POWER machines. One of the big advantages
132 of the POWER architecture. Notably more performant than PCIE Gen4, and is
133 designed to be layered on top of the physical PCIE link.
134 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
135 Truly open bi-weekly teleconference lines for anybody interested in helping
136 advance or adopting the POWER architecture.
140 ## Free Silicon Conference
142 The conference brought together experts and enthusiasts who want to build
143 a complete Free and Open Source CAD ecosystem for designing analog and
144 digital integrated circuits. The conference covered the full spectrum of
145 the design process, from system architecture, to layout and verification.
147 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
149 * LIP6's Coriolis - a set of backend design tools:
150 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
152 Note: The rest of LIP6's website is in French, but there is a UK flag
153 in the corner that gives the English version.
155 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
157 # The OpenROAD Project
159 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
160 layout generation flow (RTL-to-GDS).
162 * <https://theopenroadproject.org/>
164 # Other RISC-V GPU attempts
166 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
168 * <http://bjump.org/manycore/>
170 * <https://resharma.github.io/RISCV32-GPU/>
172 TODO: Get in touch and discuss collaboration
174 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
178 RISC-V Foundation is in the process of creating an official conformance
179 test. It's still in development as far as I can tell.
181 * //TODO LINK TO RISC-V CONFORMANCE TEST
183 ## IEEE 754 Testing/Emulation
185 IEEE 754 has no official tests for floating-point but there are
186 well-known third party tools to check such as John Hauser's TestFloat.
188 There is also his SoftFloat library, which is a software emulation library for IEEE 754.
190 * <http://www.jhauser.us/arithmetic/>
192 Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings:
194 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
195 * Crate: <https://crates.io/crates/simple-soft-float>
196 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
198 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
199 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
201 * Direct link to PDF:
202 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
206 OpenCL Conformance Tests
208 * <https://github.com/KhronosGroup/OpenCL-CTS>
210 Vulkan Conformance Tests
212 * <https://github.com/KhronosGroup/VK-GL-CTS>
214 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
215 the Khronos standards until we actually make an official submission,
216 do the paperwork, and pay the relevant fees.
218 ## Formal Verification
220 Formal verification of Libre RISC-V ensures that it is bug-free in
221 regards to what we specify. Of course, it is important to do the formal
222 verification as a final step in the development process before we produce
223 thousands or millions of silicon.
225 Some learning resources I found in the community:
227 * ZipCPU: <http://zipcpu.com/>
229 ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
232 * Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
234 <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
236 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
240 * <https://www.ohwr.org/project/wishbone-gen>
244 ## Adding new instructions:
246 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
250 * <https://danluu.com/branch-prediction/>
254 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
255 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
256 An SOC builder written in Python Migen DSL. Allows you to generate functional
257 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
258 and parameterizeable CSRs.
259 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
260 * [Minerva](https://github.com/lambdaconcept/minerva)
261 An SOC written in Python nMigen DSL
263 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
264 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
265 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
269 * <https://wiki.f-si.org/index.php/FSiC2019>
271 # Real/Physical Projects
272 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
273 * <https://chips4makers.io/blog/>
274 * <https://hackaday.io/project/7817-zynqberry>
275 * <https://github.com/efabless/raven-picorv32>
276 * <https://efabless.com>
277 * <https://efabless.com/design_catalog/default>
278 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
279 * <https://mshahrad.github.io/openpiton-asplos16.html>
282 * <https://toyota-ai.ventures/>
283 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
285 # Good Programming/Design Practices
286 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
287 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
288 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
289 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
293 * <https://youtu.be/o5Ihqg72T3c>
294 * <http://flopoco.gforge.inria.fr/>
295 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
298 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
302 * <https://github.com/Isotel/mixedsim>
303 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
304 * <http://ngspice.sourceforge.net/adms.html>
305 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
307 # Libre-RISC-V Standards
309 This list auto-generated from a page tag "standards":
311 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
315 [[resources/server-setup/web-server]]
317 [[resources/server-setup/git-mirroring]]
319 [[resources/server-setup/nagios-monitoring]]