1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 ## Overview of the user ISA:
26 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 ## OpenPOWER OpenFSI Spec (2016)
30 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
32 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
36 * <https://www.reddit.com/r/OpenPOWER/>
37 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
38 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
43 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
47 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
49 # RISC-V Instruction Set Architecture
51 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
54 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
55 of the project implies, we will be following the RISC-V ISA I due to it
56 being open-source and also because of the huge software and hardware
57 ecosystem building around it. There are other open-source ISAs but none
58 of them have the same momentum and energy behind it as RISC-V.
60 To fully take advantage of the RISC-V ecosystem, it is important to be
61 compliant with the RISC-V standards. Doing so will allow us to to reuse
62 most software as-is and avoid major forks.
64 * [Official compiled PDFs of RISC-V ISA Manual]
65 (https://github.com/riscv/riscv-isa-manual/releases/latest)
66 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
67 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
68 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
70 Note: As far as I know, we aren't using the RISC-V V Extension directly
71 at the moment (correction: we were never going to). However, there are many wiki pages that make a reference
72 to the V extension so it would be good to include it here as a reference
73 for comparative/informative purposes with regard to Simple-V.
74 <https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
77 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
81 ## D-Cache Possible Optimizations papers and links
82 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
84 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
85 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
86 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
89 # RTL Arithmetic SQRT, FPU etc.
91 ## Wallace vs Dadda Multipliers
93 * [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
96 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
97 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
98 * [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
99 * [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
102 ## CORDIC and related algorithms
104 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
105 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
106 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
107 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
108 - Does not have an easy way of computing tan(x)
109 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
110 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
111 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
112 * <https://dspguru.com/dsp/faqs/cordic/>
114 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
116 Almost all modern computers follow the IEEE Floating-Point Standard. Of
117 course, we will follow it as well for interoperability.
119 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
121 Note: Even though this is such an important standard used by everyone,
122 it is unfortunately not freely available and requires a payment to
123 access. However, each of the Libre RISC-V members already have access
126 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
128 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
130 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
132 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
134 ## Past FPU Mistakes to learn from
136 * [Intel Underestimates Error Bounds by 1.3 quintillion on
137 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
138 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
139 * How not to design an ISA
140 <https://player.vimeo.com/video/450406346>
141 Meester Forsyth <http://eelpi.gotdns.org/>
144 The Khronos Group creates open standards for authoring and acceleration
145 of graphics, media, and computation. It is a requirement for our hybrid
146 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
147 in order to be commercially-competitive in both areas: especially Vulkan
148 and OpenCL being the most important. SPIR-V is also important for the
151 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
152 switching between different accuracy levels, in userspace applications.
154 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
156 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
157 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
158 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
160 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
162 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
164 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
166 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
167 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
168 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
170 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
172 * [Announcement video](https://youtu.be/h0_syTg6TtY)
173 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
175 Note: We are implementing hardware accelerated Vulkan and
176 OpenCL while relying on other software projects to translate APIs to
177 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
179 # Graphics and Compute API Stack
181 I found this informative post that mentions Kazan and a whole bunch of
182 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
183 although performance is not evaluated.
185 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
187 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
189 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
191 # 3D Graphics Texture compression software and hardware
193 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
195 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
197 # Various POWER Communities
198 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
199 The T2080 is a POWER8 chip.
200 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
201 Supporting/Raising awareness of various POWER related open projects on the FOSS
203 - [OpenPOWER](https://openpowerfoundation.org)
204 Promotes and ensure compliance with the Power ISA amongst members.
205 - [OpenCapi](https://opencapi.org)
206 High performance interconnect for POWER machines. One of the big advantages
207 of the POWER architecture. Notably more performant than PCIE Gen4, and is
208 designed to be layered on top of the physical PCIE link.
209 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
210 Truly open bi-weekly teleconference lines for anybody interested in helping
211 advance or adopting the POWER architecture.
215 ## Free Silicon Conference
217 The conference brought together experts and enthusiasts who want to build
218 a complete Free and Open Source CAD ecosystem for designing analog and
219 digital integrated circuits. The conference covered the full spectrum of
220 the design process, from system architecture, to layout and verification.
222 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
224 * LIP6's Coriolis - a set of backend design tools:
225 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
227 Note: The rest of LIP6's website is in French, but there is a UK flag
228 in the corner that gives the English version.
230 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
232 # The OpenROAD Project
234 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
235 layout generation flow (RTL-to-GDS).
237 * <https://theopenroadproject.org/>
239 # Other RISC-V GPU attempts
241 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
243 * <http://bjump.org/manycore/>
245 * <https://resharma.github.io/RISCV32-GPU/>
247 TODO: Get in touch and discuss collaboration
249 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
253 RISC-V Foundation is in the process of creating an official conformance
254 test. It's still in development as far as I can tell.
256 * //TODO LINK TO RISC-V CONFORMANCE TEST
258 ## IEEE 754 Testing/Emulation
260 IEEE 754 has no official tests for floating-point but there are
261 well-known third party tools to check such as John Hauser's TestFloat.
263 There is also his SoftFloat library, which is a software emulation
264 library for IEEE 754.
266 * <http://www.jhauser.us/arithmetic/>
268 Jacob is also working on an IEEE 754 software emulation library written
269 in Rust which also has Python bindings:
271 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
272 * Crate: <https://crates.io/crates/simple-soft-float>
273 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
275 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
276 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
278 * Direct link to PDF:
279 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
283 OpenCL Conformance Tests
285 * <https://github.com/KhronosGroup/OpenCL-CTS>
287 Vulkan Conformance Tests
289 * <https://github.com/KhronosGroup/VK-GL-CTS>
291 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
292 the Khronos standards until we actually make an official submission,
293 do the paperwork, and pay the relevant fees.
295 ## Formal Verification
297 Formal verification of Libre RISC-V ensures that it is bug-free in
298 regards to what we specify. Of course, it is important to do the formal
299 verification as a final step in the development process before we produce
300 thousands or millions of silicon.
302 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
304 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
306 Some learning resources I found in the community:
308 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
309 tutorial for beginners and many exercises/quizzes/slides:
310 <http://zipcpu.com/tutorial/>
311 * Western Digital's SweRV CPU blog (I recommend looking at all their
312 posts): <https://tomverbeure.github.io/>
313 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
314 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
318 * <https://www.ohwr.org/project/wishbone-gen>
322 ## Adding new instructions:
324 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
328 * <https://danluu.com/branch-prediction/>
332 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
333 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
334 An SOC builder written in Python Migen DSL. Allows you to generate functional
335 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
336 and parameterizeable CSRs.
337 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
338 * There is a great guy, Robert Baruch, who has a good
339 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
340 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
341 [the code](https://github.com/RobertBaruch/n6800) and
342 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
344 * [Minerva](https://github.com/lambdaconcept/minerva)
345 An SOC written in Python nMigen DSL
346 * Minerva example using nmigen-soc
347 <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
348 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
349 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
350 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
354 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
355 * <https://codeberg.org/tok/librecell> Libre Cell Library
356 * <https://wiki.f-si.org/index.php/FSiC2019>
357 * <https://fusesoc.net>
358 * <https://www.lowrisc.org/open-silicon/>
359 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
360 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
361 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
362 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
363 ever know which to use? by Clifford E. Cummings
364 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
365 Clock Domain Crossing (CDC) Design & Verification Techniques Using
366 SystemVerilog, by Clifford E. Cummings
367 In particular, see section 5.8.2: Multi-bit CDC signal passing using
368 1-deep / 2-register FIFO synchronizer.
369 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
370 Understanding Latency Hiding on GPUs, by Vasily Volkov
371 * Efabless "Openlane" <https://github.com/efabless/openlane>
372 * Co-simulation plugin for verilator, transferring to ECP5
373 <https://github.com/vmware/cascade>
374 * Multi-read/write ported memories
375 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
376 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
377 <https://arxiv.org/pdf/1803.06185.pdf>
378 * OpenPOWER Foundation Membership
379 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
380 * Clock switching (and formal verification)
381 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
382 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
383 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
384 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
385 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
386 # Real/Physical Projects
388 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
389 * <https://chips4makers.io/blog/>
390 * <https://hackaday.io/project/7817-zynqberry>
391 * <https://github.com/efabless/raven-picorv32>
392 * <https://efabless.com>
393 * <https://efabless.com/design_catalog/default>
394 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
395 * <https://mshahrad.github.io/openpiton-asplos16.html>
397 # ASIC tape-out pricing
399 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
403 * <https://toyota-ai.ventures/>
404 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
406 # Good Programming/Design Practices
408 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
409 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
410 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
411 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
413 * <https://youtu.be/o5Ihqg72T3c>
414 * <http://flopoco.gforge.inria.fr/>
415 * Fundamentals of Modern VLSI Devices
416 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
420 * <https://www.crnhq.org/cr-kit/>
424 * <https://github.com/Isotel/mixedsim>
425 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
426 * <http://ngspice.sourceforge.net/adms.html>
427 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
429 # Libre-SOC Standards
431 This list auto-generated from a page tag "standards":
433 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
437 * [[resources/server-setup/web-server]]
438 * [[resources/server-setup/git-mirroring]]
439 * [[resources/server-setup/nagios-monitoring]]
443 * <https://www.fed4fire.eu/testbeds/>
445 # Really Useful Stuff
447 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
448 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
452 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
453 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
454 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
455 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
456 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
457 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
459 # CircuitJS experiments
461 * [[resources/high-speed-serdes-in-circuitjs]]
464 * <https://github.com/dkilfoyle/logic2>
465 [Live web version](https://dkilfoyle.github.io/logic2/)
468 > 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
469 > 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
470 > 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
471 > 4. Schematic visualisation courtesy of d3-hwschematic
472 > 5. Testbench simulation with graphical trace output and schematic animation
473 > 6. Circuit description as gates, boolean logic or verilog behavioural model
474 > 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
476 [from the GitHub page. As of 2021/03/29]
478 # ASIC Timing and Design flow resources
480 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
481 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
482 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
483 * <https://en.wikipedia.org/wiki/Frequency_divider>
485 # Geometric Haskell Library
487 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
488 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
489 * <https://arxiv.org/pdf/1501.06511.pdf>
490 * <https://bivector.net/index.html>