1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
23 * Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
25 ## Overview of the user ISA:
27 * [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 * Power ISA listings <https://power-isa-beta.mybluemix.net/>
30 ## OpenPOWER OpenFSI Spec (2016)
32 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
34 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
36 # Energy-efficient cores
38 * https://arxiv.org/abs/2002.10143
40 # Open Access Publication locations
42 * <https://open-research-europe.ec.europa.eu/browse/engineering-and-technology>
46 * <https://www.reddit.com/r/OpenPOWER/>
47 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
48 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
49 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
53 * EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
54 * https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
56 # Other GPU Specifications
59 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
60 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
62 * [Nyuzi](https://github.com/jbush001/NyuziProcessor)
68 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
72 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
75 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
79 - [A Primer on Memory Consistency and Cache Coherence
80 ](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
82 ## D-Cache Possible Optimizations papers and links
83 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
84 - [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
85 Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
87 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
88 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
89 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
92 # RTL Arithmetic SQRT, FPU etc.
94 ## Wallace vs Dadda Multipliers
96 * [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
99 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
100 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
101 * [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
102 * [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
105 ## CORDIC and related algorithms
107 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
108 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
109 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
110 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
111 - Does not have an easy way of computing tan(x)
112 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
113 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
114 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
115 * <https://dspguru.com/dsp/faqs/cordic/>
117 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
119 Almost all modern computers follow the IEEE Floating-Point Standard. Of
120 course, we will follow it as well for interoperability.
122 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
124 Note: Even though this is such an important standard used by everyone,
125 it is unfortunately not freely available and requires a payment to
126 access. However, each of the Libre-SOC members already have access
129 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
131 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
133 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
135 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
137 ## Past FPU Mistakes to learn from
139 * [Intel Underestimates Error Bounds by 1.3 quintillion on
140 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
141 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
142 * How not to design an ISA
143 <https://player.vimeo.com/video/450406346>
144 Meester Forsyth <http://eelpi.gotdns.org/>
148 The Khronos Group creates open standards for authoring and acceleration
149 of graphics, media, and computation. It is a requirement for our hybrid
150 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
151 in order to be commercially-competitive in both areas: especially Vulkan
152 and OpenCL being the most important. SPIR-V is also important for the
155 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
156 switching between different accuracy levels, in userspace applications.
158 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
160 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
161 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
162 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
164 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
166 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
168 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
170 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
171 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
172 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
174 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
176 * [Announcement video](https://youtu.be/h0_syTg6TtY)
177 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
179 Note: We are implementing hardware accelerated Vulkan and
180 OpenCL while relying on other software projects to translate APIs to
181 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
183 # Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
185 https://github.com/Microsoft/DirectX-Specs
187 # Graphics and Compute API Stack
189 I found this informative post that mentions Kazan and a whole bunch of
190 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
191 although performance is not evaluated.
193 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
195 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
197 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
199 # 3D Graphics Texture compression software and hardware
201 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
203 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
205 # Various POWER Communities
206 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
207 The T2080 is a POWER8 chip.
208 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
209 Supporting/Raising awareness of various POWER related open projects on the FOSS
211 - [OpenPOWER](https://openpowerfoundation.org)
212 Promotes and ensure compliance with the Power ISA amongst members.
213 - [OpenCapi](https://opencapi.org)
214 High performance interconnect for POWER machines. One of the big advantages
215 of the POWER architecture. Notably more performant than PCIE Gen4, and is
216 designed to be layered on top of the physical PCIE link.
217 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
218 Truly open bi-weekly teleconference lines for anybody interested in helping
219 advance or adopting the POWER architecture.
228 * LIP6's Coriolis - a set of backend design tools:
229 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
231 Note: The rest of LIP6's website is in French, but there is a UK flag
232 in the corner that gives the English version.
234 # Logical Equivalence and extraction
237 * CVC https://github.com/d-m-bailey/cvc
241 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
245 * https://nazca-design.org/convert-image-to-gds/
247 # The OpenROAD Project
249 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
250 layout generation flow (RTL-to-GDS).
252 * <https://theopenroadproject.org/>
254 # Other RISC-V GPU attempts
256 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
258 * <http://bjump.org/manycore/>
260 * <https://resharma.github.io/RISCV32-GPU/>
262 TODO: Get in touch and discuss collaboration
264 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
268 RISC-V Foundation is in the process of creating an official conformance
269 test. It's still in development as far as I can tell.
271 * //TODO LINK TO RISC-V CONFORMANCE TEST
273 ## IEEE 754 Testing/Emulation
275 IEEE 754 has no official tests for floating-point but there are
276 well-known third party tools to check such as John Hauser's TestFloat.
278 There is also his SoftFloat library, which is a software emulation
279 library for IEEE 754.
281 * <http://www.jhauser.us/arithmetic/>
283 Jacob is also working on an IEEE 754 software emulation library written
284 in Rust which also has Python bindings:
286 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
287 * Crate: <https://crates.io/crates/simple-soft-float>
288 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
290 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
291 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
293 * Direct link to PDF:
294 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
298 OpenCL Conformance Tests
300 * <https://github.com/KhronosGroup/OpenCL-CTS>
302 Vulkan Conformance Tests
304 * <https://github.com/KhronosGroup/VK-GL-CTS>
306 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
307 the Khronos standards until we actually make an official submission,
308 do the paperwork, and pay the relevant fees.
310 ## Formal Verification
312 Formal verification of Libre RISC-V ensures that it is bug-free in
313 regards to what we specify. Of course, it is important to do the formal
314 verification as a final step in the development process before we produce
315 thousands or millions of silicon.
317 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
319 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
320 * Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
323 Some learning resources I found in the community:
325 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
326 tutorial for beginners and many exercises/quizzes/slides:
327 <http://zipcpu.com/tutorial/>
328 * Western Digital's SweRV CPU blog (I recommend looking at all their
329 posts): <https://tomverbeure.github.io/>
330 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
331 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
335 * Formal verification of a fully IEEE compliant floating point unit
336 <https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
337 * <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
338 * the PVS/hw subfolder is under the 2-clause BSD license:
339 <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
340 * <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
344 * <https://www.ohwr.org/project/wishbone-gen>
348 * Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
349 * CXM <https://www.computeexpresslink.org/download-the-specification>
353 * THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
356 * MRISC32 <https://github.com/mrisc32/mrisc32>
360 ## Adding new instructions:
362 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
366 * <https://danluu.com/branch-prediction/>
370 * <https://ieeexplore.ieee.org/document/9591456> pylog fpga
371 <https://github.com/hst10/pylog>
372 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
373 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
374 * There is a great guy, Robert Baruch, who has a good
375 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
376 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
377 [the code](https://github.com/RobertBaruch/n6800) and
378 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
380 There is now a page [[docs/learning_nmigen]].
381 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
382 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
386 * <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
387 * Cray-1 Pocket Reference
388 <https://nitter.it/aka_pugs/status/1546576975166201856>
389 <https://ftp.libre-soc.org/cray-1-pocket-ref/>
390 <https://www.computerhistory.org/collections/catalog/102685876>
391 * <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
392 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
393 * <https://codeberg.org/tok/librecell> Libre Cell Library
394 * <https://wiki.f-si.org/index.php/FSiC2019>
395 * <https://fusesoc.net>
396 * <https://www.lowrisc.org/open-silicon/>
397 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
398 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
399 * <https://github.com/Ben1152000/sootty> - console-based vcd viewer
400 * <https://github.com/ics-jku/wal> - Waveform Analysis
401 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
402 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
403 ever know which to use? by Clifford E. Cummings
404 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
405 Clock Domain Crossing (CDC) Design & Verification Techniques Using
406 SystemVerilog, by Clifford E. Cummings
407 In particular, see section 5.8.2: Multi-bit CDC signal passing using
408 1-deep / 2-register FIFO synchronizer.
409 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
410 Understanding Latency Hiding on GPUs, by Vasily Volkov
411 * Efabless "Openlane" <https://github.com/efabless/openlane>
412 * example of openlane with nmigen
413 <https://github.com/lethalbit/nmigen/tree/openlane>
414 * Co-simulation plugin for verilator, transferring to ECP5
415 <https://github.com/vmware/cascade>
416 * Multi-read/write ported memories
417 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
418 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
419 <https://arxiv.org/pdf/1803.06185.pdf>
420 * OpenPOWER Foundation Membership
421 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
422 * Clock switching (and formal verification)
423 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
424 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
425 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
426 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
427 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
428 * adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
429 * ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
431 # Real/Physical Projects
433 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
434 * <https://chips4makers.io/blog/>
435 * <https://hackaday.io/project/7817-zynqberry>
436 * <https://github.com/efabless/raven-picorv32>
437 * <https://efabless.com>
438 * <https://efabless.com/design_catalog/default>
439 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
440 * <https://mshahrad.github.io/openpiton-asplos16.html>
442 # ASIC tape-out pricing
444 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
448 * <https://toyota-ai.ventures/>
449 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
451 # Good Programming/Design Practices
453 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
454 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
455 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
456 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
458 * <https://youtu.be/o5Ihqg72T3c>
459 * <http://flopoco.gforge.inria.fr/>
460 * Fundamentals of Modern VLSI Devices
461 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
465 * <https://www.crnhq.org/cr-kit/>
469 * <https://github.com/Isotel/mixedsim>
470 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
471 * <http://ngspice.sourceforge.net/adms.html>
472 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
474 # Libre-SOC Standards
476 This list auto-generated from a page tag "standards":
478 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
482 * [[resources/server-setup/web-server]]
483 * [[resources/server-setup/git-mirroring]]
484 * [[resources/server-setup/nagios-monitoring]]
488 * <https://www.fed4fire.eu/testbeds/>
490 # Really Useful Stuff
492 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
493 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
497 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
498 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
499 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
500 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
501 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
502 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
504 # CircuitJS experiments
506 * [[resources/high-speed-serdes-in-circuitjs]]
509 * <https://github.com/dkilfoyle/logic2>
510 [Live web version](https://dkilfoyle.github.io/logic2/)
513 > 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
514 > 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
515 > 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
516 > 4. Schematic visualisation courtesy of d3-hwschematic
517 > 5. Testbench simulation with graphical trace output and schematic animation
518 > 6. Circuit description as gates, boolean logic or verilog behavioural model
519 > 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
521 [from the GitHub page. As of 2021/03/29]
523 # ASIC Timing and Design flow resources
525 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
526 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
527 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
528 * <https://en.wikipedia.org/wiki/Frequency_divider>
530 # Geometric Haskell Library
532 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
533 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
534 * <https://arxiv.org/pdf/1501.06511.pdf>
535 * <https://bivector.net/index.html>
537 # Handy Compiler Algorithms for SimpleV
539 Requires aligned registers:
540 * [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
542 * [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
547 https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
548 https://github.com/idea-fasoc/OpenFASOC
549 https://www.quicklogic.com/2020/06/18/the-tipping-point/
550 https://www.quicklogic.com/blog/
551 https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
552 https://www.quicklogic.com/qorc/
553 https://en.wikipedia.org/wiki/RAD750
554 The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
555 https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
556 https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
557 https://github.com/olofk/edalize
558 https://github.com/hdl/containers
559 https://twitter.com/OlofKindgren/status/1374848733746192394
560 You might also want to check out https://umarcor.github.io/osvb/index.html
561 https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
562 “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
563 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
564 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
565 FuseSoC is used by MicroWatt and Western Digital cores
566 OpenTitan also uses FuseSoC
568 https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
569 https://cirosantilli.com/x86-paging
570 https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
571 http://denninginstitute.com/modules/vm/red/i486page.html