1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
23 * Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
25 ## Overview of the user ISA:
27 * [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 * Power ISA listings <https://power-isa-beta.mybluemix.net/>
30 ## OpenPOWER OpenFSI Spec (2016)
32 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
34 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
36 # Energy-efficient cores
38 * https://arxiv.org/abs/2002.10143
40 # Open Access Publication locations
42 * <https://open-research-europe.ec.europa.eu/browse/engineering-and-technology>
46 * <https://www.reddit.com/r/OpenPOWER/>
47 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
48 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
49 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
53 * EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
54 * https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
55 * v2.1.5 <https://openpowerfoundation.org/specifications/64bitelfabi/>
59 * <https://www.tdx.cat/bitstream/handle/10803/674224/TCRL1de1.pdf> Vector registers may be
60 made "ultra-wide" (SX Aurora / Cray)
62 # Other GPU Specifications
65 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
66 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
68 * [Nyuzi](https://github.com/jbush001/NyuziProcessor)
74 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
78 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
81 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
85 - [A Primer on Memory Consistency and Cache Coherence
86 ](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
88 ## D-Cache Possible Optimizations papers and links
89 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
90 - [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
91 Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
93 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
94 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
95 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
98 # RTL Arithmetic SQRT, FPU etc.
100 ## Wallace vs Dadda Multipliers
102 * [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
105 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
106 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
107 * [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
108 * [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
111 ## CORDIC and related algorithms
113 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
114 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
115 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
116 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
117 - Does not have an easy way of computing tan(x)
118 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
119 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
120 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
121 * <https://dspguru.com/dsp/faqs/cordic/>
123 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
125 Almost all modern computers follow the IEEE Floating-Point Standard. Of
126 course, we will follow it as well for interoperability.
128 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
130 Note: Even though this is such an important standard used by everyone,
131 it is unfortunately not freely available and requires a payment to
132 access. However, each of the Libre-SOC members already have access
135 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
137 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
139 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
141 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
143 ## Past FPU Mistakes to learn from
145 * [Intel Underestimates Error Bounds by 1.3 quintillion on
146 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
147 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
148 * How not to design an ISA
149 <https://player.vimeo.com/video/450406346>
150 Meester Forsyth <http://eelpi.gotdns.org/>
154 The Khronos Group creates open standards for authoring and acceleration
155 of graphics, media, and computation. It is a requirement for our hybrid
156 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
157 in order to be commercially-competitive in both areas: especially Vulkan
158 and OpenCL being the most important. SPIR-V is also important for the
161 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
162 switching between different accuracy levels, in userspace applications.
164 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
166 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
167 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
168 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
170 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
172 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
174 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
176 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
177 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
178 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
180 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
182 * [Announcement video](https://youtu.be/h0_syTg6TtY)
183 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
185 Note: We are implementing hardware accelerated Vulkan and
186 OpenCL while relying on other software projects to translate APIs to
187 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
189 # Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
191 https://github.com/Microsoft/DirectX-Specs
193 # Graphics and Compute API Stack
195 I found this informative post that mentions Kazan and a whole bunch of
196 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
197 although performance is not evaluated.
199 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
201 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
203 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
205 # 3D Graphics Texture compression software and hardware
207 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
209 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
211 # Various POWER Communities
212 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
213 The T2080 is a POWER8 chip.
214 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
215 Supporting/Raising awareness of various POWER related open projects on the FOSS
217 - [OpenPOWER](https://openpowerfoundation.org)
218 Promotes and ensure compliance with the Power ISA amongst members.
219 - [OpenCapi](https://opencapi.org)
220 High performance interconnect for POWER machines. One of the big advantages
221 of the POWER architecture. Notably more performant than PCIE Gen4, and is
222 designed to be layered on top of the physical PCIE link.
223 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
224 Truly open bi-weekly teleconference lines for anybody interested in helping
225 advance or adopting the POWER architecture.
234 * LIP6's Coriolis - a set of backend design tools:
235 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
237 Note: The rest of LIP6's website is in French, but there is a UK flag
238 in the corner that gives the English version.
240 # Logical Equivalence and extraction
243 * CVC https://github.com/d-m-bailey/cvc
247 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
251 * https://nazca-design.org/convert-image-to-gds/
253 # The OpenROAD Project
255 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
256 layout generation flow (RTL-to-GDS).
258 * <https://theopenroadproject.org/>
260 # Other RISC-V GPU attempts
262 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
264 * <http://bjump.org/manycore/>
266 * <https://resharma.github.io/RISCV32-GPU/>
268 TODO: Get in touch and discuss collaboration
270 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
274 RISC-V Foundation is in the process of creating an official conformance
275 test. It's still in development as far as I can tell.
277 * //TODO LINK TO RISC-V CONFORMANCE TEST
279 ## IEEE 754 Testing/Emulation
281 IEEE 754 has no official tests for floating-point but there are
282 well-known third party tools to check such as John Hauser's TestFloat.
284 There is also his SoftFloat library, which is a software emulation
285 library for IEEE 754.
287 * <http://www.jhauser.us/arithmetic/>
289 Jacob is also working on an IEEE 754 software emulation library written
290 in Rust which also has Python bindings:
292 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
293 * Crate: <https://crates.io/crates/simple-soft-float>
294 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
296 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
297 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
299 * Direct link to PDF:
300 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
304 OpenCL Conformance Tests
306 * <https://github.com/KhronosGroup/OpenCL-CTS>
308 Vulkan Conformance Tests
310 * <https://github.com/KhronosGroup/VK-GL-CTS>
312 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
313 the Khronos standards until we actually make an official submission,
314 do the paperwork, and pay the relevant fees.
316 ## Formal Verification
318 Formal verification of Libre RISC-V ensures that it is bug-free in
319 regards to what we specify. Of course, it is important to do the formal
320 verification as a final step in the development process before we produce
321 thousands or millions of silicon.
323 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
325 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
326 * Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
329 Some learning resources I found in the community:
331 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
332 tutorial for beginners and many exercises/quizzes/slides:
333 <http://zipcpu.com/tutorial/>
334 * Western Digital's SweRV CPU blog (I recommend looking at all their
335 posts): <https://tomverbeure.github.io/>
336 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
337 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
341 * Formal verification of a fully IEEE compliant floating point unit
342 <https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
343 * <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
344 * the PVS/hw subfolder is under the 2-clause BSD license:
345 <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
346 * <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
350 * <https://www.ohwr.org/project/wishbone-gen>
354 * Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
355 * CXM <https://www.computeexpresslink.org/download-the-specification>
359 * THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
362 * MRISC32 <https://github.com/mrisc32/mrisc32>
366 ## Adding new instructions:
368 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
372 * <https://danluu.com/branch-prediction/>
376 * <https://ieeexplore.ieee.org/document/9591456> pylog fpga
377 <https://github.com/hst10/pylog>
378 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
379 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
380 * There is a great guy, Robert Baruch, who has a good
381 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
382 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
383 [the code](https://github.com/RobertBaruch/n6800) and
384 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
386 There is now a page [[docs/learning_nmigen]].
387 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
388 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
392 * <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
393 * Cray-1 Pocket Reference
394 <https://nitter.it/aka_pugs/status/1546576975166201856>
395 <https://ftp.libre-soc.org/cray-1-pocket-ref/>
396 <https://www.computerhistory.org/collections/catalog/102685876>
397 * <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
398 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
399 * <https://codeberg.org/tok/librecell> Libre Cell Library
400 * <https://wiki.f-si.org/index.php/FSiC2019>
401 * <https://fusesoc.net>
402 * <https://www.lowrisc.org/open-silicon/>
403 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
404 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
405 * <https://github.com/Ben1152000/sootty> - console-based vcd viewer
406 * <https://github.com/ics-jku/wal> - Waveform Analysis
407 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
408 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
409 ever know which to use? by Clifford E. Cummings
410 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
411 Clock Domain Crossing (CDC) Design & Verification Techniques Using
412 SystemVerilog, by Clifford E. Cummings
413 In particular, see section 5.8.2: Multi-bit CDC signal passing using
414 1-deep / 2-register FIFO synchronizer.
415 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
416 Understanding Latency Hiding on GPUs, by Vasily Volkov
417 * Efabless "Openlane" <https://github.com/efabless/openlane>
418 * example of openlane with nmigen
419 <https://github.com/lethalbit/nmigen/tree/openlane>
420 * Co-simulation plugin for verilator, transferring to ECP5
421 <https://github.com/vmware/cascade>
422 * Multi-read/write ported memories
423 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
424 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
425 <https://arxiv.org/pdf/1803.06185.pdf>
426 * OpenPOWER Foundation Membership
427 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
428 * Clock switching (and formal verification)
429 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
430 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
431 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
432 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
433 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
434 * adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
435 * ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
437 # Real/Physical Projects
439 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
440 * <https://chips4makers.io/blog/>
441 * <https://hackaday.io/project/7817-zynqberry>
442 * <https://github.com/efabless/raven-picorv32>
443 * <https://efabless.com>
444 * <https://efabless.com/design_catalog/default>
445 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
446 * <https://mshahrad.github.io/openpiton-asplos16.html>
448 # ASIC tape-out pricing
450 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
454 * <https://toyota-ai.ventures/>
455 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
457 # Good Programming/Design Practices
459 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
460 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
461 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
462 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
464 * <https://youtu.be/o5Ihqg72T3c>
465 * <http://flopoco.gforge.inria.fr/>
466 * Fundamentals of Modern VLSI Devices
467 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
471 * <https://www.crnhq.org/cr-kit/>
475 * <https://github.com/Isotel/mixedsim>
476 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
477 * <http://ngspice.sourceforge.net/adms.html>
478 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
480 # Libre-SOC Standards
482 This list auto-generated from a page tag "standards":
484 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
488 * [[resources/server-setup/web-server]]
489 * [[resources/server-setup/git-mirroring]]
490 * [[resources/server-setup/nagios-monitoring]]
494 * <https://www.fed4fire.eu/testbeds/>
496 # Really Useful Stuff
498 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
499 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
503 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
504 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
505 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
506 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
507 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
508 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
510 # CircuitJS experiments
512 * [[resources/high-speed-serdes-in-circuitjs]]
515 * <https://github.com/dkilfoyle/logic2>
516 [Live web version](https://dkilfoyle.github.io/logic2/)
519 > 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
520 > 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
521 > 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
522 > 4. Schematic visualisation courtesy of d3-hwschematic
523 > 5. Testbench simulation with graphical trace output and schematic animation
524 > 6. Circuit description as gates, boolean logic or verilog behavioural model
525 > 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
527 [from the GitHub page. As of 2021/03/29]
529 # ASIC Timing and Design flow resources
531 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
532 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
533 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
534 * <https://en.wikipedia.org/wiki/Frequency_divider>
536 # Geometric Haskell Library
538 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
539 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
540 * <https://arxiv.org/pdf/1501.06511.pdf>
541 * <https://bivector.net/index.html>
543 # Handy Compiler Algorithms for SimpleV
545 Requires aligned registers:
546 * [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
548 * [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
553 https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
554 https://github.com/idea-fasoc/OpenFASOC
555 https://www.quicklogic.com/2020/06/18/the-tipping-point/
556 https://www.quicklogic.com/blog/
557 https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
558 https://www.quicklogic.com/qorc/
559 https://en.wikipedia.org/wiki/RAD750
560 The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
561 https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
562 https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
563 https://github.com/olofk/edalize
564 https://github.com/hdl/containers
565 https://twitter.com/OlofKindgren/status/1374848733746192394
566 You might also want to check out https://umarcor.github.io/osvb/index.html
567 https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
568 “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
569 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
570 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
571 FuseSoC is used by MicroWatt and Western Digital cores
572 OpenTitan also uses FuseSoC
574 https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
575 https://cirosantilli.com/x86-paging
576 https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
577 http://denninginstitute.com/modules/vm/red/i486page.html