1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 ## Overview of the user ISA:
26 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 # RISC-V Instruction Set Architecture
30 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
33 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
34 of the project implies, we will be following the RISC-V ISA I due to it
35 being open-source and also because of the huge software and hardware
36 ecosystem building around it. There are other open-source ISAs but none
37 of them have the same momentum and energy behind it as RISC-V.
39 To fully take advantage of the RISC-V ecosystem, it is important to be
40 compliant with the RISC-V standards. Doing so will allow us to to reuse
41 most software as-is and avoid major forks.
43 * [Official compiled PDFs of RISC-V ISA Manual]
44 (https://github.com/riscv/riscv-isa-manual/releases/latest)
45 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
46 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
47 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
49 Note: As far as I know, we aren't using the RISC-V V Extension directly
50 at the moment. However, there are many wiki pages that make a reference
51 to the V extension so it would be good to include it here as a reference
52 for comparative/informative purposes with regard to Simple-V.
55 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
58 # RTL Arithmetic SQRT, FPU etc.
61 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
62 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
64 ## CORDIC and related algorithms
65 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
66 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
67 - Does not have an easy way of computing tan(x)
68 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
69 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
71 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
73 Almost all modern computers follow the IEEE Floating-Point Standard. Of
74 course, we will follow it as well for interoperability.
76 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
78 Note: Even though this is such an important standard used by everyone,
79 it is unfortunately not freely available and requires a payment to
80 access. However, each of the Libre RISC-V members already have access
83 ## Past FPU Mistakes to learn from
85 * [Intel Underestimates Error Bounds by 1.3 quintillion on
86 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
87 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
91 The Khronos Group creates open standards for authoring and acceleration
92 of graphics, media, and computation. It is a requirement for our hybrid
93 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
94 in order to be commercially-competitive in both areas: especially Vulkan
95 and OpenCL being the most important. SPIR-V is also important for the
98 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
99 switching between different accuracy levels, in userspace applications.
101 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
103 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
104 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
105 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
107 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
109 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
111 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
113 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
114 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
115 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
117 Note: We are implementing hardware accelerated Vulkan and
118 OpenCL while relying on other software projects to translate APIs to
119 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
121 # Graphics and Compute API Stack
123 I found this informative post that mentions Kazan and a whole bunch of
124 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
125 although performance is not evaluated.
127 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
129 # Various POWER Communities
130 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
131 The T2080 is a POWER8 chip.
132 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
133 Supporting/Raising awareness of various POWER related open projects on the FOSS
135 - [OpenPOWER](https://openpowerfoundation.org)
136 Promotes and ensure compliance with the Power ISA amongst members.
137 - [OpenCapi](https://opencapi.org)
138 High performance interconnect for POWER machines. One of the big advantages
139 of the POWER architecture. Notably more performant than PCIE Gen4, and is
140 designed to be layered on top of the physical PCIE link.
141 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
142 Truly open bi-weekly teleconference lines for anybody interested in helping
143 advance or adopting the POWER architecture.
147 ## Free Silicon Conference
149 The conference brought together experts and enthusiasts who want to build
150 a complete Free and Open Source CAD ecosystem for designing analog and
151 digital integrated circuits. The conference covered the full spectrum of
152 the design process, from system architecture, to layout and verification.
154 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
156 * LIP6's Coriolis - a set of backend design tools:
157 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
159 Note: The rest of LIP6's website is in French, but there is a UK flag
160 in the corner that gives the English version.
162 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
164 # The OpenROAD Project
166 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
167 layout generation flow (RTL-to-GDS).
169 * <https://theopenroadproject.org/>
171 # Other RISC-V GPU attempts
173 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
175 * <http://bjump.org/manycore/>
177 * <https://resharma.github.io/RISCV32-GPU/>
179 TODO: Get in touch and discuss collaboration
181 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
185 RISC-V Foundation is in the process of creating an official conformance
186 test. It's still in development as far as I can tell.
188 * //TODO LINK TO RISC-V CONFORMANCE TEST
190 ## IEEE 754 Testing/Emulation
192 IEEE 754 has no official tests for floating-point but there are
193 well-known third party tools to check such as John Hauser's TestFloat.
195 There is also his SoftFloat library, which is a software emulation library for IEEE 754.
197 * <http://www.jhauser.us/arithmetic/>
199 Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings:
201 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
202 * Crate: <https://crates.io/crates/simple-soft-float>
203 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
205 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
206 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
208 * Direct link to PDF:
209 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
213 OpenCL Conformance Tests
215 * <https://github.com/KhronosGroup/OpenCL-CTS>
217 Vulkan Conformance Tests
219 * <https://github.com/KhronosGroup/VK-GL-CTS>
221 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
222 the Khronos standards until we actually make an official submission,
223 do the paperwork, and pay the relevant fees.
225 ## Formal Verification
227 Formal verification of Libre RISC-V ensures that it is bug-free in
228 regards to what we specify. Of course, it is important to do the formal
229 verification as a final step in the development process before we produce
230 thousands or millions of silicon.
232 Some learning resources I found in the community:
234 * ZipCPU: <http://zipcpu.com/>
236 ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
239 * Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
241 <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
243 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
247 * <https://www.ohwr.org/project/wishbone-gen>
251 ## Adding new instructions:
253 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
257 * <https://danluu.com/branch-prediction/>
261 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
262 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
263 An SOC builder written in Python Migen DSL. Allows you to generate functional
264 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
265 and parameterizeable CSRs.
266 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
268 * There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put [the code](https://github.com/RobertBaruch/n6800) and [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online.
270 * [Minerva](https://github.com/lambdaconcept/minerva)
271 An SOC written in Python nMigen DSL
273 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
274 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
275 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
279 * <https://wiki.f-si.org/index.php/FSiC2019>
281 # Real/Physical Projects
282 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
283 * <https://chips4makers.io/blog/>
284 * <https://hackaday.io/project/7817-zynqberry>
285 * <https://github.com/efabless/raven-picorv32>
286 * <https://efabless.com>
287 * <https://efabless.com/design_catalog/default>
288 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
289 * <https://mshahrad.github.io/openpiton-asplos16.html>
292 * <https://toyota-ai.ventures/>
293 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
295 # Good Programming/Design Practices
296 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
297 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
298 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
299 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
303 * <https://youtu.be/o5Ihqg72T3c>
304 * <http://flopoco.gforge.inria.fr/>
305 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
308 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
312 * <https://github.com/Isotel/mixedsim>
313 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
314 * <http://ngspice.sourceforge.net/adms.html>
315 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
317 # Libre-RISC-V Standards
319 This list auto-generated from a page tag "standards":
321 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
325 [[resources/server-setup/web-server]]
327 [[resources/server-setup/git-mirroring]]
329 [[resources/server-setup/nagios-monitoring]]