1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 ## Overview of the user ISA:
26 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 ## OpenPOWER OpenFSI Spec (2016)
30 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
32 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
34 # RISC-V Instruction Set Architecture
36 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
39 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
40 of the project implies, we will be following the RISC-V ISA I due to it
41 being open-source and also because of the huge software and hardware
42 ecosystem building around it. There are other open-source ISAs but none
43 of them have the same momentum and energy behind it as RISC-V.
45 To fully take advantage of the RISC-V ecosystem, it is important to be
46 compliant with the RISC-V standards. Doing so will allow us to to reuse
47 most software as-is and avoid major forks.
49 * [Official compiled PDFs of RISC-V ISA Manual]
50 (https://github.com/riscv/riscv-isa-manual/releases/latest)
51 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
52 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
53 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
55 Note: As far as I know, we aren't using the RISC-V V Extension directly
56 at the moment. However, there are many wiki pages that make a reference
57 to the V extension so it would be good to include it here as a reference
58 for comparative/informative purposes with regard to Simple-V.
61 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
65 ## D-Cache Possible Optimizations papers and links
66 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
68 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
69 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
70 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
73 # RTL Arithmetic SQRT, FPU etc.
76 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
77 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
79 ## CORDIC and related algorithms
81 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
82 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
83 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
84 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
85 - Does not have an easy way of computing tan(x)
86 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
87 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
88 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
90 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
92 Almost all modern computers follow the IEEE Floating-Point Standard. Of
93 course, we will follow it as well for interoperability.
95 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
97 Note: Even though this is such an important standard used by everyone,
98 it is unfortunately not freely available and requires a payment to
99 access. However, each of the Libre RISC-V members already have access
102 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
104 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
106 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
108 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
110 ## Past FPU Mistakes to learn from
112 * [Intel Underestimates Error Bounds by 1.3 quintillion on
113 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
114 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
118 The Khronos Group creates open standards for authoring and acceleration
119 of graphics, media, and computation. It is a requirement for our hybrid
120 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
121 in order to be commercially-competitive in both areas: especially Vulkan
122 and OpenCL being the most important. SPIR-V is also important for the
125 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
126 switching between different accuracy levels, in userspace applications.
128 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
130 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
131 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
132 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
134 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
136 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
138 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
140 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
141 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
142 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
144 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
146 * [Announcement video](https://youtu.be/h0_syTg6TtY)
147 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
149 Note: We are implementing hardware accelerated Vulkan and
150 OpenCL while relying on other software projects to translate APIs to
151 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
153 # Graphics and Compute API Stack
155 I found this informative post that mentions Kazan and a whole bunch of
156 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
157 although performance is not evaluated.
159 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
161 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
163 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
166 # Various POWER Communities
167 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
168 The T2080 is a POWER8 chip.
169 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
170 Supporting/Raising awareness of various POWER related open projects on the FOSS
172 - [OpenPOWER](https://openpowerfoundation.org)
173 Promotes and ensure compliance with the Power ISA amongst members.
174 - [OpenCapi](https://opencapi.org)
175 High performance interconnect for POWER machines. One of the big advantages
176 of the POWER architecture. Notably more performant than PCIE Gen4, and is
177 designed to be layered on top of the physical PCIE link.
178 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
179 Truly open bi-weekly teleconference lines for anybody interested in helping
180 advance or adopting the POWER architecture.
184 ## Free Silicon Conference
186 The conference brought together experts and enthusiasts who want to build
187 a complete Free and Open Source CAD ecosystem for designing analog and
188 digital integrated circuits. The conference covered the full spectrum of
189 the design process, from system architecture, to layout and verification.
191 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
193 * LIP6's Coriolis - a set of backend design tools:
194 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
196 Note: The rest of LIP6's website is in French, but there is a UK flag
197 in the corner that gives the English version.
199 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
201 # The OpenROAD Project
203 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
204 layout generation flow (RTL-to-GDS).
206 * <https://theopenroadproject.org/>
208 # Other RISC-V GPU attempts
210 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
212 * <http://bjump.org/manycore/>
214 * <https://resharma.github.io/RISCV32-GPU/>
216 TODO: Get in touch and discuss collaboration
218 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
222 RISC-V Foundation is in the process of creating an official conformance
223 test. It's still in development as far as I can tell.
225 * //TODO LINK TO RISC-V CONFORMANCE TEST
227 ## IEEE 754 Testing/Emulation
229 IEEE 754 has no official tests for floating-point but there are
230 well-known third party tools to check such as John Hauser's TestFloat.
232 There is also his SoftFloat library, which is a software emulation
233 library for IEEE 754.
235 * <http://www.jhauser.us/arithmetic/>
237 Jacob is also working on an IEEE 754 software emulation library written
238 in Rust which also has Python bindings:
240 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
241 * Crate: <https://crates.io/crates/simple-soft-float>
242 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
244 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
245 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
247 * Direct link to PDF:
248 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
252 OpenCL Conformance Tests
254 * <https://github.com/KhronosGroup/OpenCL-CTS>
256 Vulkan Conformance Tests
258 * <https://github.com/KhronosGroup/VK-GL-CTS>
260 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
261 the Khronos standards until we actually make an official submission,
262 do the paperwork, and pay the relevant fees.
264 ## Formal Verification
266 Formal verification of Libre RISC-V ensures that it is bug-free in
267 regards to what we specify. Of course, it is important to do the formal
268 verification as a final step in the development process before we produce
269 thousands or millions of silicon.
271 Some learning resources I found in the community:
273 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
274 tutorial for beginners and many exercises/quizzes/slides:
275 <http://zipcpu.com/tutorial/>
276 * Western Digital's SweRV CPU blog (I recommend looking at all their
277 posts): <https://tomverbeure.github.io/>
278 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
279 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
283 * <https://www.ohwr.org/project/wishbone-gen>
287 ## Adding new instructions:
289 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
293 * <https://danluu.com/branch-prediction/>
297 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
298 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
299 An SOC builder written in Python Migen DSL. Allows you to generate functional
300 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
301 and parameterizeable CSRs.
302 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
303 * There is a great guy, Robert Baruch, who has a good
304 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
305 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
306 [the code](https://github.com/RobertBaruch/n6800) and
307 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
309 * [Minerva](https://github.com/lambdaconcept/minerva)
310 An SOC written in Python nMigen DSL
311 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
312 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
313 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
317 * <https://wiki.f-si.org/index.php/FSiC2019>
318 * <https://fusesoc.net>
319 * <https://www.lowrisc.org/open-silicon/>
320 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
321 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
322 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
323 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
324 ever know which to use? by Clifford E. Cummings
325 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
326 Clock Domain Crossing (CDC) Design & Verification Techniques Using
327 SystemVerilog, by Clifford E. Cummings
328 In particular, see section 5.8.2: Multi-bit CDC signal passing using
329 1-deep / 2-register FIFO synchronizer.
330 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
331 Understanding Latency Hiding on GPUs, by Vasily Volkov
332 * Efabless "Openlane" <https://github.com/efabless/openlane>
333 * Co-simulation plugin for verilator, transferring to ECP5
334 <https://github.com/vmware/cascade>
335 * Multi-read/write ported memories
336 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
339 # Real/Physical Projects
341 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
342 * <https://chips4makers.io/blog/>
343 * <https://hackaday.io/project/7817-zynqberry>
344 * <https://github.com/efabless/raven-picorv32>
345 * <https://efabless.com>
346 * <https://efabless.com/design_catalog/default>
347 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
348 * <https://mshahrad.github.io/openpiton-asplos16.html>
350 # ASIC tape-out pricing
352 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
356 * <https://toyota-ai.ventures/>
357 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
359 # Good Programming/Design Practices
361 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
362 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
363 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
364 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
366 * <https://youtu.be/o5Ihqg72T3c>
367 * <http://flopoco.gforge.inria.fr/>
368 * Fundamentals of Modern VLSI Devices
369 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
373 * <https://www.crnhq.org/cr-kit/>
377 * <https://github.com/Isotel/mixedsim>
378 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
379 * <http://ngspice.sourceforge.net/adms.html>
380 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
382 # Libre-SOC Standards
384 This list auto-generated from a page tag "standards":
386 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
390 * [[resources/server-setup/web-server]]
391 * [[resources/server-setup/git-mirroring]]
392 * [[resources/server-setup/nagios-monitoring]]
396 * <https://www.fed4fire.eu/testbeds/>
398 # Really Useful Stuff
400 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
401 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
405 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
406 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
407 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
408 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
409 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
410 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
412 # CircuitJS experiments
414 * [[resources/high-speed-serdes-in-circuitjs]]