1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
23 * Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
24 * mini functional simulator https://github.com/god-s-perfect-idiot/POWER-sim
25 * https://raw.githubusercontent.com/linuxppc/public-docs/main/ISA/PowerPC_Assembly_IBM_Programming_Environment_2.3.pdf
27 ## Overview of the user ISA:
29 * [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
30 * Power ISA listings <https://power-isa-beta.mybluemix.net/>
32 ## OpenPOWER OpenFSI Spec (2016)
34 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
36 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
38 # Energy-efficient cores
40 * https://arxiv.org/abs/2002.10143
41 * https://arxiv.org/abs/2011.08070
43 # Open Access Publication locations
45 * <https://open-research-europe.ec.europa.eu/browse/engineering-and-technology>
49 * <https://www.reddit.com/r/OpenPOWER/>
50 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
51 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
52 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
56 * EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
57 * https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
58 * v2.1.5 <https://openpowerfoundation.org/specifications/64bitelfabi/>
62 * <https://www.tdx.cat/bitstream/handle/10803/674224/TCRL1de1.pdf> Vector registers may be
63 made "ultra-wide" (SX Aurora / Cray)
65 # Other GPU Specifications
68 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
69 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
71 * [Nyuzi](https://github.com/jbush001/NyuziProcessor)
75 # Other CPUs and ISAs worth considering
77 * https://en.m.wikipedia.org/wiki/Zilog_Z380
80 https://lists.j-core.org/pipermail/j-core/
81 http://shared-ptr.com/sh_insns.html
82 * 68080 except Length-Decode is a pig for Multi-Issue
83 http://www.apollo-core.com/index.htm?page=coding&tl=1
87 * <https://packages.debian.org/search?keywords=proot>
88 * <https://github.com/stb-tester/apt2ostree>
92 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
96 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
99 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
103 - [A Primer on Memory Consistency and Cache Coherence
104 ](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
106 ## D-Cache Possible Optimizations papers and links
107 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
108 - [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
109 Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
111 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
112 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
113 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
116 # RTL Arithmetic SQRT, FPU etc.
118 ## Wallace vs Dadda Multipliers
120 * [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
123 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
124 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
125 * [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
126 * [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
129 ## CORDIC and related algorithms
131 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
132 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
133 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
134 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
135 - Does not have an easy way of computing tan(x)
136 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
137 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
138 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
139 * <https://dspguru.com/dsp/faqs/cordic/>
141 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
143 Almost all modern computers follow the IEEE Floating-Point Standard. Of
144 course, we will follow it as well for interoperability.
146 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
148 Note: Even though this is such an important standard used by everyone,
149 it is unfortunately not freely available and requires a payment to
150 access. However, each of the Libre-SOC members already have access
153 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
155 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
157 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
159 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
161 ## Past FPU Mistakes to learn from
163 * [Intel Underestimates Error Bounds by 1.3 quintillion on
164 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
165 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
166 * How not to design an ISA
167 <https://player.vimeo.com/video/450406346>
168 Meester Forsyth <http://eelpi.gotdns.org/>
172 The Khronos Group creates open standards for authoring and acceleration
173 of graphics, media, and computation. It is a requirement for our hybrid
174 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
175 in order to be commercially-competitive in both areas: especially Vulkan
176 and OpenCL being the most important. SPIR-V is also important for the
179 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
180 switching between different accuracy levels, in userspace applications.
182 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
184 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
185 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
186 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
188 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
190 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
192 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
194 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
195 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
196 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
198 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
200 * [Announcement video](https://youtu.be/h0_syTg6TtY)
201 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
203 Note: We are implementing hardware accelerated Vulkan and
204 OpenCL while relying on other software projects to translate APIs to
205 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
207 # Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
209 https://github.com/Microsoft/DirectX-Specs
211 # Graphics and Compute API Stack
213 I found this informative post that mentions Kazan and a whole bunch of
214 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
215 although performance is not evaluated.
217 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
219 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
221 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
223 # 3D Graphics Texture compression software and hardware
225 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
227 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
229 # Various POWER Communities
230 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
231 The T2080 is a POWER8 chip.
232 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
233 Supporting/Raising awareness of various POWER related open projects on the FOSS
235 - [OpenPOWER](https://openpowerfoundation.org)
236 Promotes and ensure compliance with the Power ISA amongst members.
237 - [OpenCapi](https://opencapi.org)
238 High performance interconnect for POWER machines. One of the big advantages
239 of the POWER architecture. Notably more performant than PCIE Gen4, and is
240 designed to be layered on top of the physical PCIE link.
241 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
242 Truly open bi-weekly teleconference lines for anybody interested in helping
243 advance or adopting the POWER architecture.
252 * LIP6's Coriolis - a set of backend design tools:
253 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
255 Note: The rest of LIP6's website is in French, but there is a UK flag
256 in the corner that gives the English version.
258 # Logical Equivalence and extraction
261 * CVC https://github.com/d-m-bailey/cvc
265 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
269 * https://nazca-design.org/convert-image-to-gds/
271 # The OpenROAD Project
273 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
274 layout generation flow (RTL-to-GDS).
276 * <https://theopenroadproject.org/>
278 # Other RISC-V GPU attempts
280 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
282 * <http://bjump.org/manycore/>
284 * <https://resharma.github.io/RISCV32-GPU/>
286 TODO: Get in touch and discuss collaboration
288 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
292 RISC-V Foundation is in the process of creating an official conformance
293 test. It's still in development as far as I can tell.
295 * //TODO LINK TO RISC-V CONFORMANCE TEST
297 ## IEEE 754 Testing/Emulation
299 IEEE 754 has no official tests for floating-point but there are
300 well-known third party tools to check such as John Hauser's TestFloat.
302 There is also his SoftFloat library, which is a software emulation
303 library for IEEE 754.
305 * <http://www.jhauser.us/arithmetic/>
307 Jacob is also working on an IEEE 754 software emulation library written
308 in Rust which also has Python bindings:
310 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
311 * Crate: <https://crates.io/crates/simple-soft-float>
312 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
314 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
315 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
317 * Direct link to PDF:
318 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
322 OpenCL Conformance Tests
324 * <https://github.com/KhronosGroup/OpenCL-CTS>
326 Vulkan Conformance Tests
328 * <https://github.com/KhronosGroup/VK-GL-CTS>
330 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
331 the Khronos standards until we actually make an official submission,
332 do the paperwork, and pay the relevant fees.
334 ## Formal Verification
336 Formal verification of Libre RISC-V ensures that it is bug-free in
337 regards to what we specify. Of course, it is important to do the formal
338 verification as a final step in the development process before we produce
339 thousands or millions of silicon.
341 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
343 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
344 * Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
347 Some learning resources I found in the community:
349 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
350 tutorial for beginners and many exercises/quizzes/slides:
351 <http://zipcpu.com/tutorial/>
352 * Western Digital's SweRV CPU blog (I recommend looking at all their
353 posts): <https://tomverbeure.github.io/>
354 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
355 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
359 * Formal verification of a fully IEEE compliant floating point unit
360 <https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
361 * <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
362 * the PVS/hw subfolder is under the 2-clause BSD license:
363 <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
364 * <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
368 * <https://www.ohwr.org/project/wishbone-gen>
372 * Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
373 * CXM <https://www.computeexpresslink.org/download-the-specification>
377 * THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
380 * MRISC32 <https://github.com/mrisc32/mrisc32>
384 ## Adding new instructions:
386 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
390 * <https://danluu.com/branch-prediction/>
394 * <https://ieeexplore.ieee.org/document/9591456> pylog fpga
395 <https://github.com/hst10/pylog>
396 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
397 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
398 * There is a great guy, Robert Baruch, who has a good
399 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
400 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
401 [the code](https://github.com/RobertBaruch/n6800) and
402 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
404 There is now a page [[docs/learning_nmigen]].
405 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
406 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
410 * <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
411 * Cray-1 Pocket Reference
412 <https://nitter.it/aka_pugs/status/1546576975166201856>
413 <https://ftp.libre-soc.org/cray-1-pocket-ref/>
414 <https://www.computerhistory.org/collections/catalog/102685876>
415 * <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
416 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
417 * <https://codeberg.org/tok/librecell> Libre Cell Library
418 * <https://wiki.f-si.org/index.php/FSiC2019>
419 * <https://fusesoc.net>
420 * <https://www.lowrisc.org/open-silicon/>
421 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
422 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
423 * <https://github.com/Ben1152000/sootty> - console-based vcd viewer
424 * <https://github.com/ics-jku/wal> - Waveform Analysis
425 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
426 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
427 ever know which to use? by Clifford E. Cummings
428 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
429 Clock Domain Crossing (CDC) Design & Verification Techniques Using
430 SystemVerilog, by Clifford E. Cummings
431 In particular, see section 5.8.2: Multi-bit CDC signal passing using
432 1-deep / 2-register FIFO synchronizer.
433 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
434 Understanding Latency Hiding on GPUs, by Vasily Volkov
435 * Efabless "Openlane" <https://github.com/efabless/openlane>
436 * example of openlane with nmigen
437 <https://github.com/lethalbit/nmigen/tree/openlane>
438 * Co-simulation plugin for verilator, transferring to ECP5
439 <https://github.com/vmware/cascade>
440 * Multi-read/write ported memories
441 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
442 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
443 <https://arxiv.org/pdf/1803.06185.pdf>
444 * OpenPOWER Foundation Membership
445 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
446 * Clock switching (and formal verification)
447 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
448 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
449 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
450 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
451 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
452 * adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
453 * ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
455 # Real/Physical Projects
457 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
458 * <https://chips4makers.io/blog/>
459 * <https://hackaday.io/project/7817-zynqberry>
460 * <https://github.com/efabless/raven-picorv32>
461 * <https://efabless.com>
462 * <https://efabless.com/design_catalog/default>
463 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
464 * <https://mshahrad.github.io/openpiton-asplos16.html>
466 # ASIC tape-out pricing
468 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
472 * <https://toyota-ai.ventures/>
473 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
475 # Good Programming/Design Practices
477 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
478 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
479 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
480 * [It's not a zero-sum game](https://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
482 * <https://youtu.be/o5Ihqg72T3c>
483 * <http://flopoco.gforge.inria.fr/>
484 * Fundamentals of Modern VLSI Devices
485 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
489 * <https://www.crnhq.org/cr-kit/>
493 * <https://github.com/Isotel/mixedsim>
494 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
495 * <http://ngspice.sourceforge.net/adms.html>
496 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
498 # Libre-SOC Standards
500 This list auto-generated from a page tag "standards":
502 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
506 * [[resources/server-setup/web-server]]
507 * [[resources/server-setup/git-mirroring]]
508 * [[resources/server-setup/nagios-monitoring]]
512 * <https://www.fed4fire.eu/testbeds/>
514 # Really Useful Stuff
516 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
517 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
521 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
522 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
523 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
524 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
525 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
526 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
528 # CircuitJS experiments
530 * [[resources/high-speed-serdes-in-circuitjs]]
533 * <https://github.com/dkilfoyle/logic2>
534 [Live web version](https://dkilfoyle.github.io/logic2/)
537 > 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
538 > 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
539 > 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
540 > 4. Schematic visualisation courtesy of d3-hwschematic
541 > 5. Testbench simulation with graphical trace output and schematic animation
542 > 6. Circuit description as gates, boolean logic or verilog behavioural model
543 > 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
545 [from the GitHub page. As of 2021/03/29]
547 # ASIC Timing and Design flow resources
549 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
550 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
551 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
552 * <https://en.wikipedia.org/wiki/Frequency_divider>
554 # Geometric Haskell Library
556 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
557 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
558 * <https://arxiv.org/pdf/1501.06511.pdf>
559 * <https://bivector.net/index.html>
561 # Handy Compiler Algorithms for SimpleV
563 Requires aligned registers:
565 * [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
569 * [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
574 https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
575 https://github.com/idea-fasoc/OpenFASOC
576 https://www.quicklogic.com/2020/06/18/the-tipping-point/
577 https://www.quicklogic.com/blog/
578 https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
579 https://www.quicklogic.com/qorc/
580 https://en.wikipedia.org/wiki/RAD750
581 The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
582 https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
583 https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
584 https://github.com/olofk/edalize
585 https://github.com/hdl/containers
586 https://twitter.com/OlofKindgren/status/1374848733746192394
587 You might also want to check out https://umarcor.github.io/osvb/index.html
588 https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
589 “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
590 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
591 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
592 FuseSoC is used by MicroWatt and Western Digital cores
593 OpenTitan also uses FuseSoC
595 https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
596 https://cirosantilli.com/x86-paging
597 https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
598 http://denninginstitute.com/modules/vm/red/i486page.html