1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 ## Overview of the user ISA:
26 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 ## OpenPOWER OpenFSI Spec (2016)
30 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
32 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
36 * <https://www.reddit.com/r/OpenPOWER/>
37 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
38 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
43 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
47 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
49 # RISC-V Instruction Set Architecture
51 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
54 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
55 of the project implies, we will be following the RISC-V ISA I due to it
56 being open-source and also because of the huge software and hardware
57 ecosystem building around it. There are other open-source ISAs but none
58 of them have the same momentum and energy behind it as RISC-V.
60 To fully take advantage of the RISC-V ecosystem, it is important to be
61 compliant with the RISC-V standards. Doing so will allow us to to reuse
62 most software as-is and avoid major forks.
64 * [Official compiled PDFs of RISC-V ISA Manual]
65 (https://github.com/riscv/riscv-isa-manual/releases/latest)
66 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
67 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
68 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
70 Note: As far as I know, we aren't using the RISC-V V Extension directly
71 at the moment. However, there are many wiki pages that make a reference
72 to the V extension so it would be good to include it here as a reference
73 for comparative/informative purposes with regard to Simple-V.
76 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
80 ## D-Cache Possible Optimizations papers and links
81 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
83 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
84 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
85 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
88 # RTL Arithmetic SQRT, FPU etc.
91 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
92 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
94 ## CORDIC and related algorithms
96 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
97 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
98 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
99 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
100 - Does not have an easy way of computing tan(x)
101 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
102 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
103 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
105 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
107 Almost all modern computers follow the IEEE Floating-Point Standard. Of
108 course, we will follow it as well for interoperability.
110 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
112 Note: Even though this is such an important standard used by everyone,
113 it is unfortunately not freely available and requires a payment to
114 access. However, each of the Libre RISC-V members already have access
117 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
119 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
121 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
123 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
125 ## Past FPU Mistakes to learn from
127 * [Intel Underestimates Error Bounds by 1.3 quintillion on
128 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
129 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
133 The Khronos Group creates open standards for authoring and acceleration
134 of graphics, media, and computation. It is a requirement for our hybrid
135 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
136 in order to be commercially-competitive in both areas: especially Vulkan
137 and OpenCL being the most important. SPIR-V is also important for the
140 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
141 switching between different accuracy levels, in userspace applications.
143 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
145 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
146 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
147 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
149 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
151 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
153 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
155 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
156 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
157 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
159 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
161 * [Announcement video](https://youtu.be/h0_syTg6TtY)
162 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
164 Note: We are implementing hardware accelerated Vulkan and
165 OpenCL while relying on other software projects to translate APIs to
166 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
168 # Graphics and Compute API Stack
170 I found this informative post that mentions Kazan and a whole bunch of
171 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
172 although performance is not evaluated.
174 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
176 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
178 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
180 # 3D Graphics Texture compression software and hardware
182 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
184 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
186 # Various POWER Communities
187 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
188 The T2080 is a POWER8 chip.
189 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
190 Supporting/Raising awareness of various POWER related open projects on the FOSS
192 - [OpenPOWER](https://openpowerfoundation.org)
193 Promotes and ensure compliance with the Power ISA amongst members.
194 - [OpenCapi](https://opencapi.org)
195 High performance interconnect for POWER machines. One of the big advantages
196 of the POWER architecture. Notably more performant than PCIE Gen4, and is
197 designed to be layered on top of the physical PCIE link.
198 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
199 Truly open bi-weekly teleconference lines for anybody interested in helping
200 advance or adopting the POWER architecture.
204 ## Free Silicon Conference
206 The conference brought together experts and enthusiasts who want to build
207 a complete Free and Open Source CAD ecosystem for designing analog and
208 digital integrated circuits. The conference covered the full spectrum of
209 the design process, from system architecture, to layout and verification.
211 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
213 * LIP6's Coriolis - a set of backend design tools:
214 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
216 Note: The rest of LIP6's website is in French, but there is a UK flag
217 in the corner that gives the English version.
219 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
221 # The OpenROAD Project
223 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
224 layout generation flow (RTL-to-GDS).
226 * <https://theopenroadproject.org/>
228 # Other RISC-V GPU attempts
230 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
232 * <http://bjump.org/manycore/>
234 * <https://resharma.github.io/RISCV32-GPU/>
236 TODO: Get in touch and discuss collaboration
238 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
242 RISC-V Foundation is in the process of creating an official conformance
243 test. It's still in development as far as I can tell.
245 * //TODO LINK TO RISC-V CONFORMANCE TEST
247 ## IEEE 754 Testing/Emulation
249 IEEE 754 has no official tests for floating-point but there are
250 well-known third party tools to check such as John Hauser's TestFloat.
252 There is also his SoftFloat library, which is a software emulation
253 library for IEEE 754.
255 * <http://www.jhauser.us/arithmetic/>
257 Jacob is also working on an IEEE 754 software emulation library written
258 in Rust which also has Python bindings:
260 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
261 * Crate: <https://crates.io/crates/simple-soft-float>
262 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
264 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
265 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
267 * Direct link to PDF:
268 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
272 OpenCL Conformance Tests
274 * <https://github.com/KhronosGroup/OpenCL-CTS>
276 Vulkan Conformance Tests
278 * <https://github.com/KhronosGroup/VK-GL-CTS>
280 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
281 the Khronos standards until we actually make an official submission,
282 do the paperwork, and pay the relevant fees.
284 ## Formal Verification
286 Formal verification of Libre RISC-V ensures that it is bug-free in
287 regards to what we specify. Of course, it is important to do the formal
288 verification as a final step in the development process before we produce
289 thousands or millions of silicon.
291 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
293 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
295 Some learning resources I found in the community:
297 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
298 tutorial for beginners and many exercises/quizzes/slides:
299 <http://zipcpu.com/tutorial/>
300 * Western Digital's SweRV CPU blog (I recommend looking at all their
301 posts): <https://tomverbeure.github.io/>
302 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
303 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
307 * <https://www.ohwr.org/project/wishbone-gen>
311 ## Adding new instructions:
313 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
317 * <https://danluu.com/branch-prediction/>
321 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
322 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
323 An SOC builder written in Python Migen DSL. Allows you to generate functional
324 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
325 and parameterizeable CSRs.
326 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
327 * There is a great guy, Robert Baruch, who has a good
328 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
329 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
330 [the code](https://github.com/RobertBaruch/n6800) and
331 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
333 * [Minerva](https://github.com/lambdaconcept/minerva)
334 An SOC written in Python nMigen DSL
335 * Minerva example using nmigen-soc
336 <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
337 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
338 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
339 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
343 * <https://wiki.f-si.org/index.php/FSiC2019>
344 * <https://fusesoc.net>
345 * <https://www.lowrisc.org/open-silicon/>
346 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
347 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
348 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
349 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
350 ever know which to use? by Clifford E. Cummings
351 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
352 Clock Domain Crossing (CDC) Design & Verification Techniques Using
353 SystemVerilog, by Clifford E. Cummings
354 In particular, see section 5.8.2: Multi-bit CDC signal passing using
355 1-deep / 2-register FIFO synchronizer.
356 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
357 Understanding Latency Hiding on GPUs, by Vasily Volkov
358 * Efabless "Openlane" <https://github.com/efabless/openlane>
359 * Co-simulation plugin for verilator, transferring to ECP5
360 <https://github.com/vmware/cascade>
361 * Multi-read/write ported memories
362 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
363 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
364 <https://arxiv.org/pdf/1803.06185.pdf>
365 * OpenPOWER Foundation Membership
366 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
367 * Clock switching (and formal verification)
368 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
369 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
370 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
371 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
372 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
373 # Real/Physical Projects
375 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
376 * <https://chips4makers.io/blog/>
377 * <https://hackaday.io/project/7817-zynqberry>
378 * <https://github.com/efabless/raven-picorv32>
379 * <https://efabless.com>
380 * <https://efabless.com/design_catalog/default>
381 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
382 * <https://mshahrad.github.io/openpiton-asplos16.html>
384 # ASIC tape-out pricing
386 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
390 * <https://toyota-ai.ventures/>
391 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
393 # Good Programming/Design Practices
395 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
396 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
397 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
398 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
400 * <https://youtu.be/o5Ihqg72T3c>
401 * <http://flopoco.gforge.inria.fr/>
402 * Fundamentals of Modern VLSI Devices
403 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
407 * <https://www.crnhq.org/cr-kit/>
411 * <https://github.com/Isotel/mixedsim>
412 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
413 * <http://ngspice.sourceforge.net/adms.html>
414 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
416 # Libre-SOC Standards
418 This list auto-generated from a page tag "standards":
420 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
424 * [[resources/server-setup/web-server]]
425 * [[resources/server-setup/git-mirroring]]
426 * [[resources/server-setup/nagios-monitoring]]
430 * <https://www.fed4fire.eu/testbeds/>
432 # Really Useful Stuff
434 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
435 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
439 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
440 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
441 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
442 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
443 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
444 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
446 # CircuitJS experiments
448 * [[resources/high-speed-serdes-in-circuitjs]]
450 # ASIC Timing and Design flow resources
452 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
453 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
454 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
455 * <https://en.wikipedia.org/wiki/Frequency_divider>