1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 ## Overview of the user ISA:
26 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 ## OpenPOWER OpenFSI Spec (2016)
30 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
32 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
34 # RISC-V Instruction Set Architecture
36 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
39 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
40 of the project implies, we will be following the RISC-V ISA I due to it
41 being open-source and also because of the huge software and hardware
42 ecosystem building around it. There are other open-source ISAs but none
43 of them have the same momentum and energy behind it as RISC-V.
45 To fully take advantage of the RISC-V ecosystem, it is important to be
46 compliant with the RISC-V standards. Doing so will allow us to to reuse
47 most software as-is and avoid major forks.
49 * [Official compiled PDFs of RISC-V ISA Manual]
50 (https://github.com/riscv/riscv-isa-manual/releases/latest)
51 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
52 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
53 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
55 Note: As far as I know, we aren't using the RISC-V V Extension directly
56 at the moment. However, there are many wiki pages that make a reference
57 to the V extension so it would be good to include it here as a reference
58 for comparative/informative purposes with regard to Simple-V.
61 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
65 ## D-Cache Possible Optimizations papers and links
66 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
69 # RTL Arithmetic SQRT, FPU etc.
72 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
73 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
75 ## CORDIC and related algorithms
77 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
78 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
79 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
80 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
81 - Does not have an easy way of computing tan(x)
82 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
83 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
84 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
86 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
88 Almost all modern computers follow the IEEE Floating-Point Standard. Of
89 course, we will follow it as well for interoperability.
91 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
93 Note: Even though this is such an important standard used by everyone,
94 it is unfortunately not freely available and requires a payment to
95 access. However, each of the Libre RISC-V members already have access
98 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
100 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
102 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
104 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
106 ## Past FPU Mistakes to learn from
108 * [Intel Underestimates Error Bounds by 1.3 quintillion on
109 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
110 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
114 The Khronos Group creates open standards for authoring and acceleration
115 of graphics, media, and computation. It is a requirement for our hybrid
116 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
117 in order to be commercially-competitive in both areas: especially Vulkan
118 and OpenCL being the most important. SPIR-V is also important for the
121 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
122 switching between different accuracy levels, in userspace applications.
124 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
126 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
127 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
128 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
130 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
132 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
134 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
136 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
137 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
138 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
140 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
142 * [Announcement video](https://youtu.be/h0_syTg6TtY)
143 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
145 Note: We are implementing hardware accelerated Vulkan and
146 OpenCL while relying on other software projects to translate APIs to
147 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
149 # Graphics and Compute API Stack
151 I found this informative post that mentions Kazan and a whole bunch of
152 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
153 although performance is not evaluated.
155 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
157 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
159 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
162 # Various POWER Communities
163 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
164 The T2080 is a POWER8 chip.
165 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
166 Supporting/Raising awareness of various POWER related open projects on the FOSS
168 - [OpenPOWER](https://openpowerfoundation.org)
169 Promotes and ensure compliance with the Power ISA amongst members.
170 - [OpenCapi](https://opencapi.org)
171 High performance interconnect for POWER machines. One of the big advantages
172 of the POWER architecture. Notably more performant than PCIE Gen4, and is
173 designed to be layered on top of the physical PCIE link.
174 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
175 Truly open bi-weekly teleconference lines for anybody interested in helping
176 advance or adopting the POWER architecture.
180 ## Free Silicon Conference
182 The conference brought together experts and enthusiasts who want to build
183 a complete Free and Open Source CAD ecosystem for designing analog and
184 digital integrated circuits. The conference covered the full spectrum of
185 the design process, from system architecture, to layout and verification.
187 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
189 * LIP6's Coriolis - a set of backend design tools:
190 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
192 Note: The rest of LIP6's website is in French, but there is a UK flag
193 in the corner that gives the English version.
195 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
197 # The OpenROAD Project
199 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
200 layout generation flow (RTL-to-GDS).
202 * <https://theopenroadproject.org/>
204 # Other RISC-V GPU attempts
206 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
208 * <http://bjump.org/manycore/>
210 * <https://resharma.github.io/RISCV32-GPU/>
212 TODO: Get in touch and discuss collaboration
214 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
218 RISC-V Foundation is in the process of creating an official conformance
219 test. It's still in development as far as I can tell.
221 * //TODO LINK TO RISC-V CONFORMANCE TEST
223 ## IEEE 754 Testing/Emulation
225 IEEE 754 has no official tests for floating-point but there are
226 well-known third party tools to check such as John Hauser's TestFloat.
228 There is also his SoftFloat library, which is a software emulation
229 library for IEEE 754.
231 * <http://www.jhauser.us/arithmetic/>
233 Jacob is also working on an IEEE 754 software emulation library written
234 in Rust which also has Python bindings:
236 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
237 * Crate: <https://crates.io/crates/simple-soft-float>
238 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
240 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
241 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
243 * Direct link to PDF:
244 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
248 OpenCL Conformance Tests
250 * <https://github.com/KhronosGroup/OpenCL-CTS>
252 Vulkan Conformance Tests
254 * <https://github.com/KhronosGroup/VK-GL-CTS>
256 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
257 the Khronos standards until we actually make an official submission,
258 do the paperwork, and pay the relevant fees.
260 ## Formal Verification
262 Formal verification of Libre RISC-V ensures that it is bug-free in
263 regards to what we specify. Of course, it is important to do the formal
264 verification as a final step in the development process before we produce
265 thousands or millions of silicon.
267 Some learning resources I found in the community:
269 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
270 tutorial for beginners and many exercises/quizzes/slides:
271 <http://zipcpu.com/tutorial/>
272 * Western Digital's SweRV CPU blog (I recommend looking at all their
273 posts): <https://tomverbeure.github.io/>
274 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
275 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
279 * <https://www.ohwr.org/project/wishbone-gen>
283 ## Adding new instructions:
285 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
289 * <https://danluu.com/branch-prediction/>
293 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
294 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
295 An SOC builder written in Python Migen DSL. Allows you to generate functional
296 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
297 and parameterizeable CSRs.
298 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
299 * There is a great guy, Robert Baruch, who has a good
300 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
301 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
302 [the code](https://github.com/RobertBaruch/n6800) and
303 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
305 * [Minerva](https://github.com/lambdaconcept/minerva)
306 An SOC written in Python nMigen DSL
307 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
308 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
309 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
313 * <https://wiki.f-si.org/index.php/FSiC2019>
314 * <https://fusesoc.net>
315 * <https://www.lowrisc.org/open-silicon/>
316 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
317 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
318 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
319 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
320 ever know which to use? by Clifford E. Cummings
321 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
322 Clock Domain Crossing (CDC) Design & Verification Techniques Using
323 SystemVerilog, by Clifford E. Cummings
324 In particular, see section 5.8.2: Multi-bit CDC signal passing using
325 1-deep / 2-register FIFO synchronizer.
326 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
327 Understanding Latency Hiding on GPUs, by Vasily Volkov
328 * Efabless "Openlane" <https://github.com/efabless/openlane>
329 * Co-simulation plugin for verilator, transferring to ECP5
330 <https://github.com/vmware/cascade>
333 # Real/Physical Projects
335 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
336 * <https://chips4makers.io/blog/>
337 * <https://hackaday.io/project/7817-zynqberry>
338 * <https://github.com/efabless/raven-picorv32>
339 * <https://efabless.com>
340 * <https://efabless.com/design_catalog/default>
341 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
342 * <https://mshahrad.github.io/openpiton-asplos16.html>
344 # ASIC tape-out pricing
346 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
350 * <https://toyota-ai.ventures/>
351 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
353 # Good Programming/Design Practices
355 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
356 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
357 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
358 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
360 * <https://youtu.be/o5Ihqg72T3c>
361 * <http://flopoco.gforge.inria.fr/>
362 * Fundamentals of Modern VLSI Devices
363 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
367 * <https://www.crnhq.org/cr-kit/>
371 * <https://github.com/Isotel/mixedsim>
372 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
373 * <http://ngspice.sourceforge.net/adms.html>
374 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
376 # Libre-SOC Standards
378 This list auto-generated from a page tag "standards":
380 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
384 * [[resources/server-setup/web-server]]
385 * [[resources/server-setup/git-mirroring]]
386 * [[resources/server-setup/nagios-monitoring]]
390 * <https://www.fed4fire.eu/testbeds/>
392 # Really Useful Stuff
394 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
395 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>