1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 ## Overview of the user ISA:
26 * [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
27 * Power ISA listings <https://power-isa-beta.mybluemix.net/>
29 ## OpenPOWER OpenFSI Spec (2016)
31 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
33 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
35 # Energy-efficient cores
37 * https://arxiv.org/abs/2002.10143
41 * <https://www.reddit.com/r/OpenPOWER/>
42 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
43 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
44 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
46 # Other GPU Specifications
49 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
50 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
52 * [Nyuzi](https://github.com/jbush001/NyuziProcessor)
58 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
62 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
65 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
69 - [A Primer on Memory Consistency and Cache Coherence
70 ](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
72 ## D-Cache Possible Optimizations papers and links
73 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
74 - [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
75 Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
77 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
78 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
79 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
82 # RTL Arithmetic SQRT, FPU etc.
84 ## Wallace vs Dadda Multipliers
86 * [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
89 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
90 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
91 * [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
92 * [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
95 ## CORDIC and related algorithms
97 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
98 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
99 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
100 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
101 - Does not have an easy way of computing tan(x)
102 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
103 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
104 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
105 * <https://dspguru.com/dsp/faqs/cordic/>
107 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
109 Almost all modern computers follow the IEEE Floating-Point Standard. Of
110 course, we will follow it as well for interoperability.
112 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
114 Note: Even though this is such an important standard used by everyone,
115 it is unfortunately not freely available and requires a payment to
116 access. However, each of the Libre-SOC members already have access
119 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
121 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
123 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
125 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
127 ## Past FPU Mistakes to learn from
129 * [Intel Underestimates Error Bounds by 1.3 quintillion on
130 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
131 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
132 * How not to design an ISA
133 <https://player.vimeo.com/video/450406346>
134 Meester Forsyth <http://eelpi.gotdns.org/>
138 The Khronos Group creates open standards for authoring and acceleration
139 of graphics, media, and computation. It is a requirement for our hybrid
140 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
141 in order to be commercially-competitive in both areas: especially Vulkan
142 and OpenCL being the most important. SPIR-V is also important for the
145 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
146 switching between different accuracy levels, in userspace applications.
148 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
150 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
151 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
152 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
154 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
156 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
158 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
160 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
161 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
162 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
164 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
166 * [Announcement video](https://youtu.be/h0_syTg6TtY)
167 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
169 Note: We are implementing hardware accelerated Vulkan and
170 OpenCL while relying on other software projects to translate APIs to
171 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
173 # Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
175 https://github.com/Microsoft/DirectX-Specs
177 # Graphics and Compute API Stack
179 I found this informative post that mentions Kazan and a whole bunch of
180 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
181 although performance is not evaluated.
183 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
185 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
187 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
189 # 3D Graphics Texture compression software and hardware
191 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
193 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
195 # Various POWER Communities
196 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
197 The T2080 is a POWER8 chip.
198 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
199 Supporting/Raising awareness of various POWER related open projects on the FOSS
201 - [OpenPOWER](https://openpowerfoundation.org)
202 Promotes and ensure compliance with the Power ISA amongst members.
203 - [OpenCapi](https://opencapi.org)
204 High performance interconnect for POWER machines. One of the big advantages
205 of the POWER architecture. Notably more performant than PCIE Gen4, and is
206 designed to be layered on top of the physical PCIE link.
207 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
208 Truly open bi-weekly teleconference lines for anybody interested in helping
209 advance or adopting the POWER architecture.
218 * LIP6's Coriolis - a set of backend design tools:
219 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
221 Note: The rest of LIP6's website is in French, but there is a UK flag
222 in the corner that gives the English version.
224 # Logical Equivalence and extraction
227 * CVC https://github.com/d-m-bailey/cvc
231 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
235 * https://nazca-design.org/convert-image-to-gds/
237 # The OpenROAD Project
239 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
240 layout generation flow (RTL-to-GDS).
242 * <https://theopenroadproject.org/>
244 # Other RISC-V GPU attempts
246 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
248 * <http://bjump.org/manycore/>
250 * <https://resharma.github.io/RISCV32-GPU/>
252 TODO: Get in touch and discuss collaboration
254 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
258 RISC-V Foundation is in the process of creating an official conformance
259 test. It's still in development as far as I can tell.
261 * //TODO LINK TO RISC-V CONFORMANCE TEST
263 ## IEEE 754 Testing/Emulation
265 IEEE 754 has no official tests for floating-point but there are
266 well-known third party tools to check such as John Hauser's TestFloat.
268 There is also his SoftFloat library, which is a software emulation
269 library for IEEE 754.
271 * <http://www.jhauser.us/arithmetic/>
273 Jacob is also working on an IEEE 754 software emulation library written
274 in Rust which also has Python bindings:
276 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
277 * Crate: <https://crates.io/crates/simple-soft-float>
278 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
280 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
281 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
283 * Direct link to PDF:
284 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
288 OpenCL Conformance Tests
290 * <https://github.com/KhronosGroup/OpenCL-CTS>
292 Vulkan Conformance Tests
294 * <https://github.com/KhronosGroup/VK-GL-CTS>
296 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
297 the Khronos standards until we actually make an official submission,
298 do the paperwork, and pay the relevant fees.
300 ## Formal Verification
302 Formal verification of Libre RISC-V ensures that it is bug-free in
303 regards to what we specify. Of course, it is important to do the formal
304 verification as a final step in the development process before we produce
305 thousands or millions of silicon.
307 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
309 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
310 * Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
313 Some learning resources I found in the community:
315 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
316 tutorial for beginners and many exercises/quizzes/slides:
317 <http://zipcpu.com/tutorial/>
318 * Western Digital's SweRV CPU blog (I recommend looking at all their
319 posts): <https://tomverbeure.github.io/>
320 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
321 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
325 * <https://www.ohwr.org/project/wishbone-gen>
329 * Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
330 * CXM <https://www.computeexpresslink.org/download-the-specification>
334 * THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
337 * MRISC32 <https://github.com/mrisc32/mrisc32>
341 ## Adding new instructions:
343 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
347 * <https://danluu.com/branch-prediction/>
351 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
352 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
353 An SOC builder written in Python Migen DSL. Allows you to generate functional
354 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
355 and parameterizeable CSRs.
356 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
357 * There is a great guy, Robert Baruch, who has a good
358 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
359 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
360 [the code](https://github.com/RobertBaruch/n6800) and
361 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
363 There is now a page [[docs/learning_nmigen]].
364 * [Minerva](https://github.com/lambdaconcept/minerva)
365 An SOC written in Python nMigen DSL
366 * Minerva example using nmigen-soc
367 <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
368 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
369 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
373 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
374 * <https://codeberg.org/tok/librecell> Libre Cell Library
375 * <https://wiki.f-si.org/index.php/FSiC2019>
376 * <https://fusesoc.net>
377 * <https://www.lowrisc.org/open-silicon/>
378 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
379 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
380 * <https://github.com/Ben1152000/sootty> - console-based vcd viewer
381 * <https://github.com/ics-jku/wal> - Waveform Analysis
382 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
383 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
384 ever know which to use? by Clifford E. Cummings
385 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
386 Clock Domain Crossing (CDC) Design & Verification Techniques Using
387 SystemVerilog, by Clifford E. Cummings
388 In particular, see section 5.8.2: Multi-bit CDC signal passing using
389 1-deep / 2-register FIFO synchronizer.
390 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
391 Understanding Latency Hiding on GPUs, by Vasily Volkov
392 * Efabless "Openlane" <https://github.com/efabless/openlane>
393 * example of openlane with nmigen
394 <https://github.com/lethalbit/nmigen/tree/openlane>
395 * Co-simulation plugin for verilator, transferring to ECP5
396 <https://github.com/vmware/cascade>
397 * Multi-read/write ported memories
398 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
399 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
400 <https://arxiv.org/pdf/1803.06185.pdf>
401 * OpenPOWER Foundation Membership
402 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
403 * Clock switching (and formal verification)
404 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
405 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
406 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
407 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
408 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
410 # Real/Physical Projects
412 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
413 * <https://chips4makers.io/blog/>
414 * <https://hackaday.io/project/7817-zynqberry>
415 * <https://github.com/efabless/raven-picorv32>
416 * <https://efabless.com>
417 * <https://efabless.com/design_catalog/default>
418 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
419 * <https://mshahrad.github.io/openpiton-asplos16.html>
421 # ASIC tape-out pricing
423 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
427 * <https://toyota-ai.ventures/>
428 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
430 # Good Programming/Design Practices
432 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
433 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
434 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
435 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
437 * <https://youtu.be/o5Ihqg72T3c>
438 * <http://flopoco.gforge.inria.fr/>
439 * Fundamentals of Modern VLSI Devices
440 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
444 * <https://www.crnhq.org/cr-kit/>
448 * <https://github.com/Isotel/mixedsim>
449 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
450 * <http://ngspice.sourceforge.net/adms.html>
451 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
453 # Libre-SOC Standards
455 This list auto-generated from a page tag "standards":
457 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
461 * [[resources/server-setup/web-server]]
462 * [[resources/server-setup/git-mirroring]]
463 * [[resources/server-setup/nagios-monitoring]]
467 * <https://www.fed4fire.eu/testbeds/>
469 # Really Useful Stuff
471 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
472 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
476 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
477 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
478 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
479 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
480 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
481 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
483 # CircuitJS experiments
485 * [[resources/high-speed-serdes-in-circuitjs]]
488 * <https://github.com/dkilfoyle/logic2>
489 [Live web version](https://dkilfoyle.github.io/logic2/)
492 > 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
493 > 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
494 > 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
495 > 4. Schematic visualisation courtesy of d3-hwschematic
496 > 5. Testbench simulation with graphical trace output and schematic animation
497 > 6. Circuit description as gates, boolean logic or verilog behavioural model
498 > 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
500 [from the GitHub page. As of 2021/03/29]
502 # ASIC Timing and Design flow resources
504 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
505 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
506 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
507 * <https://en.wikipedia.org/wiki/Frequency_divider>
509 # Geometric Haskell Library
511 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
512 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
513 * <https://arxiv.org/pdf/1501.06511.pdf>
514 * <https://bivector.net/index.html>
519 https://github.com/idea-fasoc/OpenFASOC
520 https://www.quicklogic.com/2020/06/18/the-tipping-point/
521 https://www.quicklogic.com/blog/
522 https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
523 https://www.quicklogic.com/qorc/
524 https://en.wikipedia.org/wiki/RAD750
525 The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
526 https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
527 https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
528 https://github.com/olofk/edalize
529 https://github.com/hdl/containers
530 https://twitter.com/OlofKindgren/status/1374848733746192394
531 You might also want to check out https://umarcor.github.io/osvb/index.html
532 https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
533 “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
534 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
535 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
536 FuseSoC is used by MicroWatt and Western Digital cores
537 OpenTitan also uses FuseSoC
539 https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
540 https://cirosantilli.com/x86-paging
541 http://denninginstitute.com/modules/vm/red/i486page.html