1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 # RISC-V Instruction Set Architecture
26 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
29 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
30 of the project implies, we will be following the RISC-V ISA I due to it
31 being open-source and also because of the huge software and hardware
32 ecosystem building around it. There are other open-source ISAs but none
33 of them have the same momentum and energy behind it as RISC-V.
35 To fully take advantage of the RISC-V ecosystem, it is important to be
36 compliant with the RISC-V standards. Doing so will allow us to to reuse
37 most software as-is and avoid major forks.
39 * [Official compiled PDFs of RISC-V ISA Manual]
40 (https://github.com/riscv/riscv-isa-manual/releases/latest)
41 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
42 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
43 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
45 Note: As far as I know, we aren't using the RISC-V V Extension directly
46 at the moment. However, there are many wiki pages that make a reference
47 to the V extension so it would be good to include it here as a reference
48 for comparative/informative purposes with regard to Simple-V.
51 # RTL Arithmetic SQRT, FPU etc.
54 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
55 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
57 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
59 Almost all modern computers follow the IEEE Floating-Point Standard. Of
60 course, we will follow it as well for interoperability.
62 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
64 Note: Even though this is such an important standard used by everyone,
65 it is unfortunately not freely available and requires a payment to
66 access. However, each of the Libre RISC-V members already have access
71 The Khronos Group creates open standards for authoring and acceleration
72 of graphics, media, and computation. It is a requirement for our hybrid
73 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
74 in order to be commercially-competitive in both areas: especially Vulkan
75 and OpenCL being the most important. SPIR-V is also important for the
78 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
79 switching between different accuracy levels, in userspace applications.
81 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
83 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
84 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
85 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
87 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
89 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
91 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
93 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
94 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
95 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
97 Note: We are implementing hardware accelerated Vulkan and
98 OpenCL while relying on other software projects to translate APIs to
99 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
101 # Graphics and Compute API Stack
103 I found this informative post that mentions Kazan and a whole bunch of
104 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
105 although performance is not evaluated.
107 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
109 # Various POWER Communities
110 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
111 I still can't figure out if its chip is POWER8 or POWER9. Please verify!
112 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
113 Supporting/Raising awareness of various POWER related open projects on the FOSS
115 - [OpenPOWER](https://openpowerfoundation.org)
116 Promotes and ensure compliance with the Power ISA amongst members.
117 - [OpenCapi](https://opencapi.org)
118 High performance interconnect for POWER machines. One of the big advantages
119 of the POWER architecture. Notably more performant than PCIE Gen4, and is
120 designed to be layered on top of the physical PCIE link.
121 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
122 Truly open bi-weekly teleconference lines for anybody interested in helping
123 advance or adopting the POWER architecture.
127 ## Free Silicon Conference
129 The conference brought together experts and enthusiasts who want to build
130 a complete Free and Open Source CAD ecosystem for designing analog and
131 digital integrated circuits. The conference covered the full spectrum of
132 the design process, from system architecture, to layout and verification.
134 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
136 * LIP6's Coriolis - a set of backend design tools:
137 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
139 Note: The rest of LIP6's website is in French, but there is a UK flag
140 in the corner that gives the English version.
142 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
144 # The OpenROAD Project
146 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
147 layout generation flow (RTL-to-GDS).
149 * <https://theopenroadproject.org/>
151 # Other RISC-V GPU attempts
153 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
155 * <http://bjump.org/manycore/>
157 * <https://resharma.github.io/RISCV32-GPU/>
159 TODO: Get in touch and discuss collaboration
161 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
165 RISC-V Foundation is in the process of creating an official conformance
166 test. It's still in development as far as I can tell.
168 * //TODO LINK TO RISC-V CONFORMANCE TEST
172 IEEE 754 has no official tests for floating-point but there are several
173 well-known third party tools to check such as John Hauser's SoftFloat
176 * <http://www.jhauser.us/arithmetic/>
178 Jacob is also making a Rust library to check IEEE 754 operations.
180 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002737.html>
182 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
183 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
185 * Direct link to PDF:
186 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
190 OpenCL Conformance Tests
192 * <https://github.com/KhronosGroup/OpenCL-CTS>
194 Vulkan Conformance Tests
196 * <https://github.com/KhronosGroup/VK-GL-CTS>
198 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
199 the Khronos standards until we actually make an official submission,
200 do the paperwork, and pay the relevant fees.
202 ## Formal Verification
204 Formal verification of Libre RISC-V ensures that it is bug-free in
205 regards to what we specify. Of course, it is important to do the formal
206 verification as a final step in the development process before we produce
207 thousands or millions of silicon.
209 Some learning resources I found in the community:
211 * ZipCPU: <http://zipcpu.com/>
213 ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
216 * Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
218 <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
220 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
224 * <https://www.ohwr.org/project/wishbone-gen>
228 ## Adding new instructions:
230 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
234 * <https://danluu.com/branch-prediction/>
238 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
239 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
240 An SOC builder written in Python Migen DSL. Allows you to generate functional
241 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
242 and parameterizeable CSRs.
243 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
244 * [Minerva](https://github.com/lambdaconcept/minerva)
245 An SOC written in Python nMigen DSL
247 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
248 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
249 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
253 * <https://wiki.f-si.org/index.php/FSiC2019>
255 # Real/Physical Projects
256 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
257 * <https://chips4makers.io/blog/>
258 * <https://hackaday.io/project/7817-zynqberry>
259 * <https://github.com/efabless/raven-picorv32>
260 * <https://efabless.com>
261 * <https://efabless.com/design_catalog/default>
262 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
263 * <https://mshahrad.github.io/openpiton-asplos16.html>
266 * <https://toyota-ai.ventures/>
267 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
269 # Good Programming/Design Practices
270 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
271 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
272 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
273 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
277 * <https://youtu.be/o5Ihqg72T3c>
278 * <http://flopoco.gforge.inria.fr/>
279 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
282 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
286 * <https://github.com/Isotel/mixedsim>
287 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
288 * <http://ngspice.sourceforge.net/adms.html>
289 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
291 # Libre-RISC-V Standards
293 This list auto-generated from a page tag "standards":
295 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
299 [[resources/server-setup/git-mirroring]]