1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
24 # RISC-V Instruction Set Architecture
26 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
29 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
30 of the project implies, we will be following the RISC-V ISA I due to it
31 being open-source and also because of the huge software and hardware
32 ecosystem building around it. There are other open-source ISAs but none
33 of them have the same momentum and energy behind it as RISC-V.
35 To fully take advantage of the RISC-V ecosystem, it is important to be
36 compliant with the RISC-V standards. Doing so will allow us to to reuse
37 most software as-is and avoid major forks.
39 * [Official compiled PDFs of RISC-V ISA Manual]
40 (https://github.com/riscv/riscv-isa-manual/releases/latest)
41 * [Working draft of the proposed RISC-V Bitmanipulation extension](https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf)
42 * [RISC-V "V" Vector Extension](https://riscv.github.io/documents/riscv-v-spec/)
43 * [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
45 Note: As far as I know, we aren't using the RISC-V V Extension directly
46 at the moment. However, there are many wiki pages that make a reference
47 to the V extension so it would be good to include it here as a reference
48 for comparative/informative purposes with regard to Simple-V.
51 # RTL Arithmetic SQRT, FPU etc.
54 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
55 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
57 ## CORDIC and related algorithms
58 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
59 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
60 - Does not have an easy way of computing tan(x)
61 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
62 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
64 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
66 Almost all modern computers follow the IEEE Floating-Point Standard. Of
67 course, we will follow it as well for interoperability.
69 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
71 Note: Even though this is such an important standard used by everyone,
72 it is unfortunately not freely available and requires a payment to
73 access. However, each of the Libre RISC-V members already have access
78 The Khronos Group creates open standards for authoring and acceleration
79 of graphics, media, and computation. It is a requirement for our hybrid
80 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
81 in order to be commercially-competitive in both areas: especially Vulkan
82 and OpenCL being the most important. SPIR-V is also important for the
85 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
86 switching between different accuracy levels, in userspace applications.
88 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
90 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
91 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
92 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
94 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
96 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
98 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
100 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
101 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
102 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
104 Note: We are implementing hardware accelerated Vulkan and
105 OpenCL while relying on other software projects to translate APIs to
106 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
108 # Graphics and Compute API Stack
110 I found this informative post that mentions Kazan and a whole bunch of
111 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
112 although performance is not evaluated.
114 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
116 # Various POWER Communities
117 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
118 The T2080 is a POWER8 chip.
119 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
120 Supporting/Raising awareness of various POWER related open projects on the FOSS
122 - [OpenPOWER](https://openpowerfoundation.org)
123 Promotes and ensure compliance with the Power ISA amongst members.
124 - [OpenCapi](https://opencapi.org)
125 High performance interconnect for POWER machines. One of the big advantages
126 of the POWER architecture. Notably more performant than PCIE Gen4, and is
127 designed to be layered on top of the physical PCIE link.
128 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
129 Truly open bi-weekly teleconference lines for anybody interested in helping
130 advance or adopting the POWER architecture.
134 ## Free Silicon Conference
136 The conference brought together experts and enthusiasts who want to build
137 a complete Free and Open Source CAD ecosystem for designing analog and
138 digital integrated circuits. The conference covered the full spectrum of
139 the design process, from system architecture, to layout and verification.
141 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
143 * LIP6's Coriolis - a set of backend design tools:
144 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
146 Note: The rest of LIP6's website is in French, but there is a UK flag
147 in the corner that gives the English version.
149 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
151 # The OpenROAD Project
153 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
154 layout generation flow (RTL-to-GDS).
156 * <https://theopenroadproject.org/>
158 # Other RISC-V GPU attempts
160 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
162 * <http://bjump.org/manycore/>
164 * <https://resharma.github.io/RISCV32-GPU/>
166 TODO: Get in touch and discuss collaboration
168 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
172 RISC-V Foundation is in the process of creating an official conformance
173 test. It's still in development as far as I can tell.
175 * //TODO LINK TO RISC-V CONFORMANCE TEST
177 ## IEEE 754 Testing/Emulation
179 IEEE 754 has no official tests for floating-point but there are
180 well-known third party tools to check such as John Hauser's TestFloat.
182 There is also his SoftFloat library, which is a software emulation library for IEEE 754.
184 * <http://www.jhauser.us/arithmetic/>
186 Jacob is also working on an IEEE 754 software emulation library written in Rust which also has Python bindings:
188 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
189 * Crate: <https://crates.io/crates/simple-soft-float>
190 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
192 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
193 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
195 * Direct link to PDF:
196 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
200 OpenCL Conformance Tests
202 * <https://github.com/KhronosGroup/OpenCL-CTS>
204 Vulkan Conformance Tests
206 * <https://github.com/KhronosGroup/VK-GL-CTS>
208 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
209 the Khronos standards until we actually make an official submission,
210 do the paperwork, and pay the relevant fees.
212 ## Formal Verification
214 Formal verification of Libre RISC-V ensures that it is bug-free in
215 regards to what we specify. Of course, it is important to do the formal
216 verification as a final step in the development process before we produce
217 thousands or millions of silicon.
219 Some learning resources I found in the community:
221 * ZipCPU: <http://zipcpu.com/>
223 ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
226 * Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
228 <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
230 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
234 * <https://www.ohwr.org/project/wishbone-gen>
238 ## Adding new instructions:
240 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
244 * <https://danluu.com/branch-prediction/>
248 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
249 * [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
250 An SOC builder written in Python Migen DSL. Allows you to generate functional
251 RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
252 and parameterizeable CSRs.
253 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
254 * [Minerva](https://github.com/lambdaconcept/minerva)
255 An SOC written in Python nMigen DSL
257 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
258 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
259 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
263 * <https://wiki.f-si.org/index.php/FSiC2019>
265 # Real/Physical Projects
266 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
267 * <https://chips4makers.io/blog/>
268 * <https://hackaday.io/project/7817-zynqberry>
269 * <https://github.com/efabless/raven-picorv32>
270 * <https://efabless.com>
271 * <https://efabless.com/design_catalog/default>
272 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
273 * <https://mshahrad.github.io/openpiton-asplos16.html>
276 * <https://toyota-ai.ventures/>
277 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
279 # Good Programming/Design Practices
280 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
281 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
282 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
283 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
287 * <https://youtu.be/o5Ihqg72T3c>
288 * <http://flopoco.gforge.inria.fr/>
289 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
292 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
296 * <https://github.com/Isotel/mixedsim>
297 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
298 * <http://ngspice.sourceforge.net/adms.html>
299 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
301 # Libre-RISC-V Standards
303 This list auto-generated from a page tag "standards":
305 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
309 [[resources/server-setup/web-server]]
311 [[resources/server-setup/git-mirroring]]
313 [[resources/server-setup/nagios-monitoring]]