1 // See LICENSE for license details.
3 #ifndef _RISCV_CACHE_SIM_H
4 #define _RISCV_CACHE_SIM_H
16 lfsr_t(const lfsr_t
& lfsr
) : reg(lfsr
.reg
) {}
17 uint32_t next() { return reg
= (reg
>>1)^(-(reg
&1) & 0xd0000001); }
25 cache_sim_t(size_t sets
, size_t ways
, size_t linesz
, const char* name
);
26 cache_sim_t(const cache_sim_t
& rhs
);
27 virtual ~cache_sim_t();
29 void access(uint64_t addr
, size_t bytes
, bool store
);
31 void set_miss_handler(cache_sim_t
* mh
) { miss_handler
= mh
; }
33 static cache_sim_t
* construct(const char* config
, const char* name
);
36 static const uint64_t VALID
= 1ULL << 63;
37 static const uint64_t DIRTY
= 1ULL << 62;
39 virtual uint64_t* check_tag(uint64_t addr
);
40 virtual uint64_t victimize(uint64_t addr
);
43 cache_sim_t
* miss_handler
;
52 uint64_t read_accesses
;
55 uint64_t write_accesses
;
56 uint64_t write_misses
;
57 uint64_t bytes_written
;
65 class fa_cache_sim_t
: public cache_sim_t
68 fa_cache_sim_t(size_t ways
, size_t linesz
, const char* name
);
69 uint64_t* check_tag(uint64_t addr
);
70 uint64_t victimize(uint64_t addr
);
72 static bool cmp(uint64_t a
, uint64_t b
);
73 std::map
<uint64_t, uint64_t> tags
;
76 class cache_memtracer_t
: public memtracer_t
79 cache_memtracer_t(const char* config
, const char* name
)
81 cache
= cache_sim_t::construct(config
, name
);
87 void set_miss_handler(cache_sim_t
* mh
)
89 cache
->set_miss_handler(mh
);
96 class icache_sim_t
: public cache_memtracer_t
99 icache_sim_t(const char* config
) : cache_memtracer_t(config
, "I$") {}
100 bool interested_in_range(uint64_t begin
, uint64_t end
, bool store
, bool fetch
)
104 void trace(uint64_t addr
, size_t bytes
, bool store
, bool fetch
)
106 if (fetch
) cache
->access(addr
, bytes
, false);
110 class dcache_sim_t
: public cache_memtracer_t
113 dcache_sim_t(const char* config
) : cache_memtracer_t(config
, "D$") {}
114 bool interested_in_range(uint64_t begin
, uint64_t end
, bool store
, bool fetch
)
118 void trace(uint64_t addr
, size_t bytes
, bool store
, bool fetch
)
120 if (!fetch
) cache
->access(addr
, bytes
, store
);