riscv/debug_defines.h

   1 #define DTM_IDCODE                          0x01
   2 /*
   3 * Identifies the release version of this part.
   4  */
   5 #define DTM_IDCODE_VERSION_OFFSET           28
   6 #define DTM_IDCODE_VERSION_LENGTH           4
   7 #define DTM_IDCODE_VERSION                  (0xf << DTM_IDCODE_VERSION_OFFSET)
   8 /*
   9 * Identifies the designer's part number of this part.
  10  */
  11 #define DTM_IDCODE_PARTNUMBER_OFFSET        12
  12 #define DTM_IDCODE_PARTNUMBER_LENGTH        16
  13 #define DTM_IDCODE_PARTNUMBER               (0xffff << DTM_IDCODE_PARTNUMBER_OFFSET)
  14 /*
  15 * Identifies the designer/manufacturer of this part. Bits 6:0 must be
  16 * bits 6:0 of the designer/manufacturer's Identification Code as
  17 * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
  18 * count of the number of continuation characters (0x7f) in that same
  19 * Identification Code.
  20  */
  21 #define DTM_IDCODE_MANUFID_OFFSET           1
  22 #define DTM_IDCODE_MANUFID_LENGTH           11
  23 #define DTM_IDCODE_MANUFID                  (0x7ff << DTM_IDCODE_MANUFID_OFFSET)
  24 #define DTM_IDCODE_1_OFFSET                 0
  25 #define DTM_IDCODE_1_LENGTH                 1
  26 #define DTM_IDCODE_1                        (0x1 << DTM_IDCODE_1_OFFSET)
  27 #define DTM_DTMCONTROL                      0x10
  28 /*
  29 * Writing 1 to this bit resets the DMI controller, clearing any
  30 * sticky error state.
  31  */
  32 #define DTM_DTMCONTROL_DMIRESET_OFFSET      16
  33 #define DTM_DTMCONTROL_DMIRESET_LENGTH      1
  34 #define DTM_DTMCONTROL_DMIRESET             (0x1 << DTM_DTMCONTROL_DMIRESET_OFFSET)
  35 /*
  36 * This is the minimum number of cycles a debugger should spend in
  37 * Run-Test/Idle after every DMI scan to avoid a 'busy'
  38 * return code (\Fdmistat of 3). A debugger must still
  39 * check \Fdmistat when necessary.
  40 *
  41 * 0: It is not necessary to enter Run-Test/Idle at all.
  42 *
  43 * 1: Enter Run-Test/Idle and leave it immediately.
  44 *
  45 * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
  46 *
  47 * And so on.
  48  */
  49 #define DTM_DTMCONTROL_IDLE_OFFSET          12
  50 #define DTM_DTMCONTROL_IDLE_LENGTH          3
  51 #define DTM_DTMCONTROL_IDLE                 (0x7 << DTM_DTMCONTROL_IDLE_OFFSET)
  52 /*
  53 * 0: No error.
  54 *
  55 * 1: Reserved. Interpret the same as 2.
  56 *
  57 * 2: An operation failed (resulted in \Fop of 2).
  58 *
  59 * 3: An operation was attempted while a DMI access was still in
  60 * progress (resulted in \Fop of 3).
  61  */
  62 #define DTM_DTMCONTROL_DMISTAT_OFFSET       10
  63 #define DTM_DTMCONTROL_DMISTAT_LENGTH       2
  64 #define DTM_DTMCONTROL_DMISTAT              (0x3 << DTM_DTMCONTROL_DMISTAT_OFFSET)
  65 /*
  66 * The size of \Faddress in \Rdmi.
  67  */
  68 #define DTM_DTMCONTROL_ABITS_OFFSET         4
  69 #define DTM_DTMCONTROL_ABITS_LENGTH         6
  70 #define DTM_DTMCONTROL_ABITS                (0x3f << DTM_DTMCONTROL_ABITS_OFFSET)
  71 /*
  72 * 0: Version described in spec version 0.11.
  73 *
  74 * 1: Version described in spec version 0.12 (and later?), which
  75 * reduces the DMI data width to 32 bits.
  76 *
  77 * Other values are reserved for future use.
  78  */
  79 #define DTM_DTMCONTROL_VERSION_OFFSET       0
  80 #define DTM_DTMCONTROL_VERSION_LENGTH       4
  81 #define DTM_DTMCONTROL_VERSION              (0xf << DTM_DTMCONTROL_VERSION_OFFSET)
  82 #define DTM_DMI                             0x11
  83 /*
  84 * Address used for DMI access. In Update-DR this value is used
  85 * to access the DM over the DMI.
  86  */
  87 #define DTM_DMI_ADDRESS_OFFSET              34
  88 #define DTM_DMI_ADDRESS_LENGTH              abits
  89 #define DTM_DMI_ADDRESS                     (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
  90 /*
  91 * The data to send to the DM over the DMI during Update-DR, and
  92 * the data returned from the DM as a result of the previous operation.
  93  */
  94 #define DTM_DMI_DATA_OFFSET                 2
  95 #define DTM_DMI_DATA_LENGTH                 32
  96 #define DTM_DMI_DATA                        (0xffffffffL << DTM_DMI_DATA_OFFSET)
  97 /*
  98 * When the debugger writes this field, it has the following meaning:
  99 *
 100 * 0: Ignore \Fdata. (nop)
 101 *
 102 * 1: Read from \Faddress. (read)
 103 *
 104 * 2: Write \Fdata to \Faddress. (write)
 105 *
 106 * 3: Reserved.
 107 *
 108 * When the debugger reads this field, it means the following:
 109 *
 110 * 0: The previous operation completed successfully.
 111 *
 112 * 1: Reserved.
 113 *
 114 * 2: A previous operation failed.  The data scanned into \Rdmi in
 115 * this access will be ignored.  This status is sticky and can be
 116 * cleared by writing \Fdmireset in \Rdtmcontrol.
 117 *
 118 * This indicates that the DM itself responded with an error, e.g.
 119 * in the System Bus and Serial Port overflow/underflow cases.
 120 *
 121 * 3: An operation was attempted while a DMI request is still in
 122 * progress. The data scanned into \Rdmi in this access will be
 123 * ignored. This status is sticky and can be cleared by writing
 124 * \Fdmireset in \Rdtmcontrol. If a debugger sees this status, it
 125 * needs to give the target more TCK edges between Update-DR and
 126 * Capture-DR. The simplest way to do that is to add extra transitions
 127 * in Run-Test/Idle.
 128 *
 129 * (The DTM, DM, and/or component may be in different clock domains,
 130 * so synchronization may be required. Some relatively fixed number of
 131 * TCK ticks may be needed for the request to reach the DM, complete,
 132 * and for the response to be synchronized back into the TCK domain.)
 133  */
 134 #define DTM_DMI_OP_OFFSET                   0
 135 #define DTM_DMI_OP_LENGTH                   2
 136 #define DTM_DMI_OP                          (0x3L << DTM_DMI_OP_OFFSET)
 137 #define CSR_DCSR                            0x7b0
 138 /*
 139 * 0: There is no external debug support.
 140 *
 141 * 1: External debug support exists as it is described in this document.
 142 *
 143 * Other values are reserved for future standards.
 144  */
 145 #define CSR_DCSR_XDEBUGVER_OFFSET           30
 146 #define CSR_DCSR_XDEBUGVER_LENGTH           2
 147 #define CSR_DCSR_XDEBUGVER                  (0x3 << CSR_DCSR_XDEBUGVER_OFFSET)
 148 /*
 149 * When 1, {\tt ebreak} instructions in Machine Mode enter Halt Mode.
 150  */
 151 #define CSR_DCSR_EBREAKM_OFFSET             15
 152 #define CSR_DCSR_EBREAKM_LENGTH             1
 153 #define CSR_DCSR_EBREAKM                    (0x1 << CSR_DCSR_EBREAKM_OFFSET)
 154 /*
 155 * When 1, {\tt ebreak} instructions in Hypervisor Mode enter Halt Mode.
 156  */
 157 #define CSR_DCSR_EBREAKH_OFFSET             14
 158 #define CSR_DCSR_EBREAKH_LENGTH             1
 159 #define CSR_DCSR_EBREAKH                    (0x1 << CSR_DCSR_EBREAKH_OFFSET)
 160 /*
 161 * When 1, {\tt ebreak} instructions in Supervisor Mode enter Halt Mode.
 162  */
 163 #define CSR_DCSR_EBREAKS_OFFSET             13
 164 #define CSR_DCSR_EBREAKS_LENGTH             1
 165 #define CSR_DCSR_EBREAKS                    (0x1 << CSR_DCSR_EBREAKS_OFFSET)
 166 /*
 167 * When 1, {\tt ebreak} instructions in User/Application Mode enter
 168 * Halt Mode.
 169  */
 170 #define CSR_DCSR_EBREAKU_OFFSET             12
 171 #define CSR_DCSR_EBREAKU_LENGTH             1
 172 #define CSR_DCSR_EBREAKU                    (0x1 << CSR_DCSR_EBREAKU_OFFSET)
 173 /*
 174 * Controls the behavior of any counters while the component is in
 175 * Halt Mode. This includes the {\tt cycle} and {\tt instret} CSRs.
 176 * When 1, counters are stopped when the component is in Halt Mode.
 177 * Otherwise, the counters continue to run.
 178 *
 179 * An implementation may choose not to support writing to this bit.
 180 * The debugger must read back the value it writes to check whether
 181 * the feature is supported.
 182  */
 183 #define CSR_DCSR_STOPCYCLE_OFFSET           10
 184 #define CSR_DCSR_STOPCYCLE_LENGTH           1
 185 #define CSR_DCSR_STOPCYCLE                  (0x1 << CSR_DCSR_STOPCYCLE_OFFSET)
 186 /*
 187 * Controls the behavior of any timers while the component is in Debug
 188 * Mode.  This includes the {\tt time} and {tt timeh} CSRs.  When 1,
 189 * timers are stopped when the component is in Halt Mode.  Otherwise,
 190 * the timers continue to run.
 191 *
 192 * An implementation may choose not to support writing to this bit.
 193 * The debugger must read back the value it writes to check whether
 194 * the feature is supported.
 195  */
 196 #define CSR_DCSR_STOPTIME_OFFSET            9
 197 #define CSR_DCSR_STOPTIME_LENGTH            1
 198 #define CSR_DCSR_STOPTIME                   (0x1 << CSR_DCSR_STOPTIME_OFFSET)
 199 /*
 200 * Explains why Halt Mode was entered.
 201 *
 202 * When there are multiple reasons to enter Halt Mode in a single
 203 * cycle, the cause with the highest priority is the one written.
 204 *
 205 * 1: A software breakpoint was hit. (priority 3)
 206 *
 207 * 2: The Trigger Module caused a halt. (priority 4)
 208 *
 209 * 3: The debug interrupt was asserted by the Debug Module. (priority 2)
 210 *
 211 * 4: The hart single stepped because \Fstep was set. (priority 1)
 212 *
 213 * 5: \Fhaltreq was set. (priority 0)
 214 *
 215 * Other values are reserved for future use.
 216  */
 217 #define CSR_DCSR_CAUSE_OFFSET               6
 218 #define CSR_DCSR_CAUSE_LENGTH               3
 219 #define CSR_DCSR_CAUSE                      (0x7 << CSR_DCSR_CAUSE_OFFSET)
 220 /*
 221 * When set and not in Halt Mode, the hart will only execute a single
 222 * instruction, and then enter Halt Mode. Interrupts are disabled
 223 * when this bit is set.
 224  */
 225 #define CSR_DCSR_STEP_OFFSET                2
 226 #define CSR_DCSR_STEP_LENGTH                1
 227 #define CSR_DCSR_STEP                       (0x1 << CSR_DCSR_STEP_OFFSET)
 228 /*
 229 * Contains the privilege level the hart was operating in when Debug
 230 * Mode was entered. The encoding is describe in Table
 231 * \ref{tab:privlevel}.  A debugger can change this value to change
 232 * the hart's privilege level when exiting Halt Mode.
 233 *
 234 * Not all privilege levels are supported on all harts. If the
 235 * encoding written is not supported or the debugger is not allowed to
 236 * change to it, the hart may change to any supported privilege level.
 237  */
 238 #define CSR_DCSR_PRV_OFFSET                 0
 239 #define CSR_DCSR_PRV_LENGTH                 2
 240 #define CSR_DCSR_PRV                        (0x3 << CSR_DCSR_PRV_OFFSET)
 241 #define CSR_DPC                             0x7b1
 242 #define CSR_DPC_DPC_OFFSET                  0
 243 #define CSR_DPC_DPC_LENGTH                  XLEN
 244 #define CSR_DPC_DPC                         (((1L<<XLEN)-1) << CSR_DPC_DPC_OFFSET)
 245 #define CSR_DSCRATCH0                       0x7b2
 246 #define CSR_DSCRATCH1                       0x7b3
 247 #define CSR_PRIV                            virtual
 248 /*
 249 * Contains the privilege level the hart was operating in when Debug
 250 * Mode was entered. The encoding is describe in Table
 251 * \ref{tab:privlevel}. A user can write this value to change the
 252 * hart's privilege level when exiting Halt Mode.
 253  */
 254 #define CSR_PRIV_PRV_OFFSET                 0
 255 #define CSR_PRIV_PRV_LENGTH                 2
 256 #define CSR_PRIV_PRV                        (0x3 << CSR_PRIV_PRV_OFFSET)
 257 #define CSR_TSELECT                         0x7a0
 258 #define CSR_TSELECT_INDEX_OFFSET            0
 259 #define CSR_TSELECT_INDEX_LENGTH            XLEN
 260 #define CSR_TSELECT_INDEX                   (((1L<<XLEN)-1) << CSR_TSELECT_INDEX_OFFSET)
 261 #define CSR_TDATA1                          0x7a1
 262 /*
 263 * 0: There is no trigger at this \Rtselect.
 264 *
 265 * 1: The trigger is a legacy SiFive address match trigger. These
 266 * should not be implemented and aren't further documented here.
 267 *
 268 * 2: The trigger is an address/data match trigger. The remaining bits
 269 * in this register act as described in \Rmcontrol.
 270 *
 271 * 3: The trigger is an instruction count trigger. The remaining bits
 272 * in this register act as described in \Ricount.
 273 *
 274 * 15: This trigger exists (so enumeration shouldn't terminate), but
 275 * is not currently available.
 276 *
 277 * Other values are reserved for future use.
 278  */
 279 #define CSR_TDATA1_TYPE_OFFSET              XLEN-4
 280 #define CSR_TDATA1_TYPE_LENGTH              4
 281 #define CSR_TDATA1_TYPE                     (0xfL << CSR_TDATA1_TYPE_OFFSET)
 282 /*
 283 * 0: Both Debug and M Mode can write the {\tt tdata} registers at the
 284 * selected \Rtselect.
 285 *
 286 * 1: Only Halt Mode can write the {\tt tdata} registers at the
 287 * selected \Rtselect.  Writes from other modes are ignored.
 288 *
 289 * This bit is only writable from Halt Mode.
 290  */
 291 #define CSR_TDATA1_HMODE_OFFSET             XLEN-5
 292 #define CSR_TDATA1_HMODE_LENGTH             1
 293 #define CSR_TDATA1_HMODE                    (0x1L << CSR_TDATA1_HMODE_OFFSET)
 294 /*
 295 * Trigger-specific data.
 296  */
 297 #define CSR_TDATA1_DATA_OFFSET              0
 298 #define CSR_TDATA1_DATA_LENGTH              XLEN - 5
 299 #define CSR_TDATA1_DATA                     (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET)
 300 #define CSR_TDATA2                          0x7a2
 301 #define CSR_TDATA2_DATA_OFFSET              0
 302 #define CSR_TDATA2_DATA_LENGTH              XLEN
 303 #define CSR_TDATA2_DATA                     (((1L<<XLEN)-1) << CSR_TDATA2_DATA_OFFSET)
 304 #define CSR_TDATA3                          0x7a3
 305 #define CSR_TDATA3_DATA_OFFSET              0
 306 #define CSR_TDATA3_DATA_LENGTH              XLEN
 307 #define CSR_TDATA3_DATA                     (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET)
 308 #define CSR_MCONTROL                        0x7a1
 309 #define CSR_MCONTROL_TYPE_OFFSET            XLEN-4
 310 #define CSR_MCONTROL_TYPE_LENGTH            4
 311 #define CSR_MCONTROL_TYPE                   (0xfL << CSR_MCONTROL_TYPE_OFFSET)
 312 #define CSR_MCONTROL_DMODE_OFFSET           XLEN-5
 313 #define CSR_MCONTROL_DMODE_LENGTH           1
 314 #define CSR_MCONTROL_DMODE                  (0x1L << CSR_MCONTROL_DMODE_OFFSET)
 315 /*
 316 * Specifies the largest naturally aligned powers-of-two (NAPOT) range
 317 * supported by the hardware. The value is the logarithm base 2 of the
 318 * number of bytes in that range.  A value of 0 indicates that only
 319 * exact value matches are supported (one byte range). A value of 63
 320 * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
 321 * size.
 322  */
 323 #define CSR_MCONTROL_MASKMAX_OFFSET         XLEN-11
 324 #define CSR_MCONTROL_MASKMAX_LENGTH         6
 325 #define CSR_MCONTROL_MASKMAX                (0x3fL << CSR_MCONTROL_MASKMAX_OFFSET)
 326 /*
 327 * 0: Perform a match on the address.
 328 *
 329 * 1: Perform a match on the data value loaded/stored, or the
 330 * instruction executed.
 331  */
 332 #define CSR_MCONTROL_SELECT_OFFSET          19
 333 #define CSR_MCONTROL_SELECT_LENGTH          1
 334 #define CSR_MCONTROL_SELECT                 (0x1L << CSR_MCONTROL_SELECT_OFFSET)
 335 /*
 336 * 0: The action for this trigger will be taken just before the
 337 * instruction that triggered it is executed, but after all preceding
 338 * instructions are are committed.
 339 *
 340 * 1: The action for this trigger will be taken after the instruction
 341 * that triggered it is executed. It should be taken before the next
 342 * instruction is executed, but it is better to implement triggers and
 343 * not implement that suggestion than to not implement them at all.
 344 *
 345 * Most hardware will only implement one timing or the other, possibly
 346 * dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit
 347 * primarily exists for the hardware to communicate to the debugger
 348 * what will happen. Hardware may implement the bit fully writable, in
 349 * which case the debugger has a little more control.
 350 *
 351 * Data load triggers with \Ftiming of 0 will result in the same load
 352 * happening again when the debugger lets the core run. For data load
 353 * triggers debuggers must first attempt to set the breakpoint with
 354 * \Ftiming of 1.
 355 *
 356 * A chain of triggers that don't all have the same \Ftiming value
 357 * will never fire (unless consecutive instructions match the
 358 * appropriate triggers).
 359  */
 360 #define CSR_MCONTROL_TIMING_OFFSET          18
 361 #define CSR_MCONTROL_TIMING_LENGTH          1
 362 #define CSR_MCONTROL_TIMING                 (0x1L << CSR_MCONTROL_TIMING_OFFSET)
 363 /*
 364 * Determines what happens when this trigger matches.
 365 *
 366 * 0: Raise a breakpoint exception. (Used when software wants to use
 367 * the trigger module without an external debugger attached.)
 368 *
 369 * 1: Enter Halt Mode. (Only supported when \Fhmode is 1.)
 370 *
 371 * 2: Start tracing.
 372 *
 373 * 3: Stop tracing.
 374 *
 375 * 4: Emit trace data for this match. If it is a data access match,
 376 * emit appropriate Load/Store Address/Data. If it is an instruction
 377 * execution, emit its PC.
 378 *
 379 * Other values are reserved for future use.
 380  */
 381 #define CSR_MCONTROL_ACTION_OFFSET          12
 382 #define CSR_MCONTROL_ACTION_LENGTH          6
 383 #define CSR_MCONTROL_ACTION                 (0x3fL << CSR_MCONTROL_ACTION_OFFSET)
 384 /*
 385 * 0: When this trigger matches, the configured action is taken.
 386 *
 387 * 1: While this trigger does not match, it prevents the trigger with
 388 * the next index from matching.
 389  */
 390 #define CSR_MCONTROL_CHAIN_OFFSET           11
 391 #define CSR_MCONTROL_CHAIN_LENGTH           1
 392 #define CSR_MCONTROL_CHAIN                  (0x1L << CSR_MCONTROL_CHAIN_OFFSET)
 393 /*
 394 * 0: Matches when the value equals \Rtdatatwo.
 395 *
 396 * 1: Matches when the top M bits of the value match the top M bits of
 397 * \Rtdatatwo. M is XLEN-1 minus the index of the least-significant
 398 * bit containing 0 in \Rtdatatwo.
 399 *
 400 * 2: Matches when the value is greater than or equal to \Rtdatatwo.
 401 *
 402 * 3: Matches when the value is less than \Rtdatatwo.
 403 *
 404 * 4: Matches when the lower half of the value equals the lower half
 405 * of \Rtdatatwo after the lower half of the value is ANDed with the
 406 * upper half of \Rtdatatwo.
 407 *
 408 * 5: Matches when the upper half of the value equals the lower half
 409 * of \Rtdatatwo after the upper half of the value is ANDed with the
 410 * upper half of \Rtdatatwo.
 411 *
 412 * Other values are reserved for future use.
 413  */
 414 #define CSR_MCONTROL_MATCH_OFFSET           7
 415 #define CSR_MCONTROL_MATCH_LENGTH           4
 416 #define CSR_MCONTROL_MATCH                  (0xfL << CSR_MCONTROL_MATCH_OFFSET)
 417 /*
 418 * When set, enable this trigger in M mode.
 419  */
 420 #define CSR_MCONTROL_M_OFFSET               6
 421 #define CSR_MCONTROL_M_LENGTH               1
 422 #define CSR_MCONTROL_M                      (0x1L << CSR_MCONTROL_M_OFFSET)
 423 /*
 424 * When set, enable this trigger in H mode.
 425  */
 426 #define CSR_MCONTROL_H_OFFSET               5
 427 #define CSR_MCONTROL_H_LENGTH               1
 428 #define CSR_MCONTROL_H                      (0x1L << CSR_MCONTROL_H_OFFSET)
 429 /*
 430 * When set, enable this trigger in S mode.
 431  */
 432 #define CSR_MCONTROL_S_OFFSET               4
 433 #define CSR_MCONTROL_S_LENGTH               1
 434 #define CSR_MCONTROL_S                      (0x1L << CSR_MCONTROL_S_OFFSET)
 435 /*
 436 * When set, enable this trigger in U mode.
 437  */
 438 #define CSR_MCONTROL_U_OFFSET               3
 439 #define CSR_MCONTROL_U_LENGTH               1
 440 #define CSR_MCONTROL_U                      (0x1L << CSR_MCONTROL_U_OFFSET)
 441 /*
 442 * When set, the trigger fires on the address or opcode of an
 443 * instruction that is executed.
 444  */
 445 #define CSR_MCONTROL_EXECUTE_OFFSET         2
 446 #define CSR_MCONTROL_EXECUTE_LENGTH         1
 447 #define CSR_MCONTROL_EXECUTE                (0x1L << CSR_MCONTROL_EXECUTE_OFFSET)
 448 /*
 449 * When set, the trigger fires on the address or data of a store.
 450  */
 451 #define CSR_MCONTROL_STORE_OFFSET           1
 452 #define CSR_MCONTROL_STORE_LENGTH           1
 453 #define CSR_MCONTROL_STORE                  (0x1L << CSR_MCONTROL_STORE_OFFSET)
 454 /*
 455 * When set, the trigger fires on the address or data of a load.
 456  */
 457 #define CSR_MCONTROL_LOAD_OFFSET            0
 458 #define CSR_MCONTROL_LOAD_LENGTH            1
 459 #define CSR_MCONTROL_LOAD                   (0x1L << CSR_MCONTROL_LOAD_OFFSET)
 460 #define CSR_ICOUNT                          0x7a1
 461 #define CSR_ICOUNT_TYPE_OFFSET              XLEN-4
 462 #define CSR_ICOUNT_TYPE_LENGTH              4
 463 #define CSR_ICOUNT_TYPE                     (0xfL << CSR_ICOUNT_TYPE_OFFSET)
 464 #define CSR_ICOUNT_DMODE_OFFSET             XLEN-5
 465 #define CSR_ICOUNT_DMODE_LENGTH             1
 466 #define CSR_ICOUNT_DMODE                    (0x1L << CSR_ICOUNT_DMODE_OFFSET)
 467 /*
 468 * When count is decremented to 0, the trigger fires. Instead of
 469 * changing \Fcount from 1 to 0, it is also acceptable for hardware to
 470 * clear \Fm, \Fh, \Fs, and \Fu. This allows \Fcount to be hard-wired
 471 * to 1 if this register just exists for single step.
 472  */
 473 #define CSR_ICOUNT_COUNT_OFFSET             10
 474 #define CSR_ICOUNT_COUNT_LENGTH             14
 475 #define CSR_ICOUNT_COUNT                    (0x3fffL << CSR_ICOUNT_COUNT_OFFSET)
 476 /*
 477 * When set, every instruction completed in M mode decrements \Fcount
 478 * by 1.
 479  */
 480 #define CSR_ICOUNT_M_OFFSET                 9
 481 #define CSR_ICOUNT_M_LENGTH                 1
 482 #define CSR_ICOUNT_M                        (0x1L << CSR_ICOUNT_M_OFFSET)
 483 /*
 484 * When set, every instruction completed in H mode decrements \Fcount
 485 * by 1.
 486  */
 487 #define CSR_ICOUNT_H_OFFSET                 8
 488 #define CSR_ICOUNT_H_LENGTH                 1
 489 #define CSR_ICOUNT_H                        (0x1L << CSR_ICOUNT_H_OFFSET)
 490 /*
 491 * When set, every instruction completed in S mode decrements \Fcount
 492 * by 1.
 493  */
 494 #define CSR_ICOUNT_S_OFFSET                 7
 495 #define CSR_ICOUNT_S_LENGTH                 1
 496 #define CSR_ICOUNT_S                        (0x1L << CSR_ICOUNT_S_OFFSET)
 497 /*
 498 * When set, every instruction completed in U mode decrements \Fcount
 499 * by 1.
 500  */
 501 #define CSR_ICOUNT_U_OFFSET                 6
 502 #define CSR_ICOUNT_U_LENGTH                 1
 503 #define CSR_ICOUNT_U                        (0x1L << CSR_ICOUNT_U_OFFSET)
 504 /*
 505 * Determines what happens when this trigger matches.
 506 *
 507 * 0: Raise a debug exception. (Used when software wants to use the
 508 * trigger module without an external debugger attached.)
 509 *
 510 * 1: Enter Halt Mode. (Only supported when \Fhmode is 1.)
 511 *
 512 * 2: Start tracing.
 513 *
 514 * 3: Stop tracing.
 515 *
 516 * 4: Emit trace data for this match. If it is a data access match,
 517 * emit appropriate Load/Store Address/Data. If it is an instruction
 518 * execution, emit its PC.
 519 *
 520 * Other values are reserved for future use.
 521  */
 522 #define CSR_ICOUNT_ACTION_OFFSET            0
 523 #define CSR_ICOUNT_ACTION_LENGTH            6
 524 #define CSR_ICOUNT_ACTION                   (0x3fL << CSR_ICOUNT_ACTION_OFFSET)
 525 #define DMI_DMCONTROL                       0x00
 526 /*
 527 * Halt request signal for the hart selected by \Fhartsel. When 1, the
 528 * hart will halt if it's not currently halted.
 529 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
 530 *
 531 * Writes apply to the new value of \Fhartsel.
 532  */
 533 #define DMI_DMCONTROL_HALTREQ_OFFSET        31
 534 #define DMI_DMCONTROL_HALTREQ_LENGTH        1
 535 #define DMI_DMCONTROL_HALTREQ               (0x1 << DMI_DMCONTROL_HALTREQ_OFFSET)
 536 /*
 537 * Resume request signal for the hart selected by \Fhartsel. When 1,
 538 * the hart will resume if it's currently halted.
 539 * Setting both \Fhaltreq and \Fresumereq leads to undefined behavior.
 540 *
 541 * Writes apply to the new value of \Fhartsel.
 542  */
 543 #define DMI_DMCONTROL_RESUMEREQ_OFFSET      30
 544 #define DMI_DMCONTROL_RESUMEREQ_LENGTH      1
 545 #define DMI_DMCONTROL_RESUMEREQ             (0x1 << DMI_DMCONTROL_RESUMEREQ_OFFSET)
 546 /*
 547 * The status of the currently selected hart.
 548 *
 549 * 0: Halted.
 550 *
 551 * 1: Running.
 552 *
 553 * 2: Unavailable (eg. powered down, held in reset).
 554 *
 555 * 3: \Fhartsel specifies a hart that does not exist in this system.
 556  */
 557 #define DMI_DMCONTROL_HARTSTATUS_OFFSET     26
 558 #define DMI_DMCONTROL_HARTSTATUS_LENGTH     2
 559 #define DMI_DMCONTROL_HARTSTATUS            (0x3 << DMI_DMCONTROL_HARTSTATUS_OFFSET)
 560 /*
 561 * The DM-specific index of the hart to select.
 562  */
 563 #define DMI_DMCONTROL_HARTSEL_OFFSET        16
 564 #define DMI_DMCONTROL_HARTSEL_LENGTH        10
 565 #define DMI_DMCONTROL_HARTSEL               (0x3ff << DMI_DMCONTROL_HARTSEL_OFFSET)
 566 /*
 567 * This optional bit controls reset to the currently selected hart. To
 568 * perform a reset the debugger writes 1, and then writes 0 to
 569 * deassert the reset signal.
 570 *
 571 * If this feature is not implemented, the bit always stays 0, so
 572 * after writing 1 the debugger can read the register back to see if
 573 * the feature is supported.
 574  */
 575 #define DMI_DMCONTROL_HARTRESET_OFFSET      10
 576 #define DMI_DMCONTROL_HARTRESET_LENGTH      1
 577 #define DMI_DMCONTROL_HARTRESET             (0x1 << DMI_DMCONTROL_HARTRESET_OFFSET)
 578 /*
 579 * This bit serves as a reset signal for the Debug Module itself.
 580 *
 581 * 0: The module, including authentication mechanism, is held in
 582 * reset.
 583 *
 584 * 1: The module functions normally.
 585 *
 586 * No other mechanism should exist that may result in resetting the
 587 * Debug Module after power up, including the platform's system reset
 588 * or Debug Transport reset signals.
 589 *
 590 * A debugger should pulse this bit low to ensure that the Debug
 591 * Module is fully reset and ready to use.
 592 *
 593 * Implementations may use this bit to aid debugging, for example by
 594 * preventing the Debug Module from being power gated while debugging
 595 * is active.
 596  */
 597 #define DMI_DMCONTROL_DMACTIVE_OFFSET       9
 598 #define DMI_DMCONTROL_DMACTIVE_LENGTH       1
 599 #define DMI_DMCONTROL_DMACTIVE              (0x1 << DMI_DMCONTROL_DMACTIVE_OFFSET)
 600 /*
 601 * This bit controls the reset signal from the DM to the rest of the
 602 * system. To perform a reset the debugger writes 1, and then writes 0
 603 * to deassert the reset.
 604  */
 605 #define DMI_DMCONTROL_RESET_OFFSET          8
 606 #define DMI_DMCONTROL_RESET_LENGTH          1
 607 #define DMI_DMCONTROL_RESET                 (0x1 << DMI_DMCONTROL_RESET_OFFSET)
 608 /*
 609 * 0 when authentication is required before using the DM.  1 when the
 610 * authentication check has passed. On components that don't implement
 611 * authentication, this bit must be preset as 1.
 612  */
 613 #define DMI_DMCONTROL_AUTHENTICATED_OFFSET  7
 614 #define DMI_DMCONTROL_AUTHENTICATED_LENGTH  1
 615 #define DMI_DMCONTROL_AUTHENTICATED         (0x1 << DMI_DMCONTROL_AUTHENTICATED_OFFSET)
 616 /*
 617 * 0: The authentication module is ready to process the next
 618 * read/write to \Rauthdata.
 619 *
 620 * 1: The authentication module is busy. Accessing \Rauthdata results
 621 * in unspecified behavior.
 622 *
 623 * \Fauthbusy only becomes set in immediate response to an access to
 624 * \Rauthdata.
 625  */
 626 #define DMI_DMCONTROL_AUTHBUSY_OFFSET       6
 627 #define DMI_DMCONTROL_AUTHBUSY_LENGTH       1
 628 #define DMI_DMCONTROL_AUTHBUSY              (0x1 << DMI_DMCONTROL_AUTHBUSY_OFFSET)
 629 /*
 630 * 0: There is no Debug Module present.
 631 *
 632 * 1: There is a Debug Module and it conforms to version 0.12 of this
 633 * specification.
 634 *
 635 * Other values are reserved for future use.
 636  */
 637 #define DMI_DMCONTROL_VERSION_OFFSET        0
 638 #define DMI_DMCONTROL_VERSION_LENGTH        4
 639 #define DMI_DMCONTROL_VERSION               (0xf << DMI_DMCONTROL_VERSION_OFFSET)
 640 #define DMI_HARTINFO                        0x01
 641 /*
 642 * 0: The {\tt data} registers are shadowed in the hart by CSR
 643 * registers. Each CSR register is XLEN bits in size, and corresponds
 644 * to a single argument, per Table~\ref{tab:datareg}.
 645 *
 646 * 1: The {\tt data} registers are shadowed in the hart's memory map.
 647 * Each register takes up 4 bytes in the memory map.
 648  */
 649 #define DMI_HARTINFO_DATAACCESS_OFFSET      16
 650 #define DMI_HARTINFO_DATAACCESS_LENGTH      1
 651 #define DMI_HARTINFO_DATAACCESS             (0x1 << DMI_HARTINFO_DATAACCESS_OFFSET)
 652 /*
 653 * If \Fdataaccess is 0: Number of CSR registers dedicated to
 654 * shadowing the {\tt data} registers.
 655 *
 656 * If \Fdataaccess is 1: Number of 32-bit words in the memory map
 657 * dedicated to shadowing the {\tt data} registers.
 658  */
 659 #define DMI_HARTINFO_DATASIZE_OFFSET        12
 660 #define DMI_HARTINFO_DATASIZE_LENGTH        4
 661 #define DMI_HARTINFO_DATASIZE               (0xf << DMI_HARTINFO_DATASIZE_OFFSET)
 662 /*
 663 * If \Fdataaccess is 0: The number of the first CSR dedicated to
 664 * shadowing the {\tt data} registers.
 665 *
 666 * If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
 667 * registers are shadowed.
 668  */
 669 #define DMI_HARTINFO_DATAADDR_OFFSET        0
 670 #define DMI_HARTINFO_DATAADDR_LENGTH        12
 671 #define DMI_HARTINFO_DATAADDR               (0xfff << DMI_HARTINFO_DATAADDR_OFFSET)
 672 #define DMI_HALTSUM                         0x02
 673 #define DMI_HALTSUM_HALT1023_992_OFFSET     31
 674 #define DMI_HALTSUM_HALT1023_992_LENGTH     1
 675 #define DMI_HALTSUM_HALT1023_992            (0x1 << DMI_HALTSUM_HALT1023_992_OFFSET)
 676 #define DMI_HALTSUM_HALT991_960_OFFSET      30
 677 #define DMI_HALTSUM_HALT991_960_LENGTH      1
 678 #define DMI_HALTSUM_HALT991_960             (0x1 << DMI_HALTSUM_HALT991_960_OFFSET)
 679 #define DMI_HALTSUM_HALT959_928_OFFSET      29
 680 #define DMI_HALTSUM_HALT959_928_LENGTH      1
 681 #define DMI_HALTSUM_HALT959_928             (0x1 << DMI_HALTSUM_HALT959_928_OFFSET)
 682 #define DMI_HALTSUM_HALT927_896_OFFSET      28
 683 #define DMI_HALTSUM_HALT927_896_LENGTH      1
 684 #define DMI_HALTSUM_HALT927_896             (0x1 << DMI_HALTSUM_HALT927_896_OFFSET)
 685 #define DMI_HALTSUM_HALT895_864_OFFSET      27
 686 #define DMI_HALTSUM_HALT895_864_LENGTH      1
 687 #define DMI_HALTSUM_HALT895_864             (0x1 << DMI_HALTSUM_HALT895_864_OFFSET)
 688 #define DMI_HALTSUM_HALT863_832_OFFSET      26
 689 #define DMI_HALTSUM_HALT863_832_LENGTH      1
 690 #define DMI_HALTSUM_HALT863_832             (0x1 << DMI_HALTSUM_HALT863_832_OFFSET)
 691 #define DMI_HALTSUM_HALT831_800_OFFSET      25
 692 #define DMI_HALTSUM_HALT831_800_LENGTH      1
 693 #define DMI_HALTSUM_HALT831_800             (0x1 << DMI_HALTSUM_HALT831_800_OFFSET)
 694 #define DMI_HALTSUM_HALT799_768_OFFSET      24
 695 #define DMI_HALTSUM_HALT799_768_LENGTH      1
 696 #define DMI_HALTSUM_HALT799_768             (0x1 << DMI_HALTSUM_HALT799_768_OFFSET)
 697 #define DMI_HALTSUM_HALT767_736_OFFSET      23
 698 #define DMI_HALTSUM_HALT767_736_LENGTH      1
 699 #define DMI_HALTSUM_HALT767_736             (0x1 << DMI_HALTSUM_HALT767_736_OFFSET)
 700 #define DMI_HALTSUM_HALT735_704_OFFSET      22
 701 #define DMI_HALTSUM_HALT735_704_LENGTH      1
 702 #define DMI_HALTSUM_HALT735_704             (0x1 << DMI_HALTSUM_HALT735_704_OFFSET)
 703 #define DMI_HALTSUM_HALT703_672_OFFSET      21
 704 #define DMI_HALTSUM_HALT703_672_LENGTH      1
 705 #define DMI_HALTSUM_HALT703_672             (0x1 << DMI_HALTSUM_HALT703_672_OFFSET)
 706 #define DMI_HALTSUM_HALT671_640_OFFSET      20
 707 #define DMI_HALTSUM_HALT671_640_LENGTH      1
 708 #define DMI_HALTSUM_HALT671_640             (0x1 << DMI_HALTSUM_HALT671_640_OFFSET)
 709 #define DMI_HALTSUM_HALT639_608_OFFSET      19
 710 #define DMI_HALTSUM_HALT639_608_LENGTH      1
 711 #define DMI_HALTSUM_HALT639_608             (0x1 << DMI_HALTSUM_HALT639_608_OFFSET)
 712 #define DMI_HALTSUM_HALT607_576_OFFSET      18
 713 #define DMI_HALTSUM_HALT607_576_LENGTH      1
 714 #define DMI_HALTSUM_HALT607_576             (0x1 << DMI_HALTSUM_HALT607_576_OFFSET)
 715 #define DMI_HALTSUM_HALT575_544_OFFSET      17
 716 #define DMI_HALTSUM_HALT575_544_LENGTH      1
 717 #define DMI_HALTSUM_HALT575_544             (0x1 << DMI_HALTSUM_HALT575_544_OFFSET)
 718 #define DMI_HALTSUM_HALT543_512_OFFSET      16
 719 #define DMI_HALTSUM_HALT543_512_LENGTH      1
 720 #define DMI_HALTSUM_HALT543_512             (0x1 << DMI_HALTSUM_HALT543_512_OFFSET)
 721 #define DMI_HALTSUM_HALT511_480_OFFSET      15
 722 #define DMI_HALTSUM_HALT511_480_LENGTH      1
 723 #define DMI_HALTSUM_HALT511_480             (0x1 << DMI_HALTSUM_HALT511_480_OFFSET)
 724 #define DMI_HALTSUM_HALT479_448_OFFSET      14
 725 #define DMI_HALTSUM_HALT479_448_LENGTH      1
 726 #define DMI_HALTSUM_HALT479_448             (0x1 << DMI_HALTSUM_HALT479_448_OFFSET)
 727 #define DMI_HALTSUM_HALT447_416_OFFSET      13
 728 #define DMI_HALTSUM_HALT447_416_LENGTH      1
 729 #define DMI_HALTSUM_HALT447_416             (0x1 << DMI_HALTSUM_HALT447_416_OFFSET)
 730 #define DMI_HALTSUM_HALT415_384_OFFSET      12
 731 #define DMI_HALTSUM_HALT415_384_LENGTH      1
 732 #define DMI_HALTSUM_HALT415_384             (0x1 << DMI_HALTSUM_HALT415_384_OFFSET)
 733 #define DMI_HALTSUM_HALT383_352_OFFSET      11
 734 #define DMI_HALTSUM_HALT383_352_LENGTH      1
 735 #define DMI_HALTSUM_HALT383_352             (0x1 << DMI_HALTSUM_HALT383_352_OFFSET)
 736 #define DMI_HALTSUM_HALT351_320_OFFSET      10
 737 #define DMI_HALTSUM_HALT351_320_LENGTH      1
 738 #define DMI_HALTSUM_HALT351_320             (0x1 << DMI_HALTSUM_HALT351_320_OFFSET)
 739 #define DMI_HALTSUM_HALT319_288_OFFSET      9
 740 #define DMI_HALTSUM_HALT319_288_LENGTH      1
 741 #define DMI_HALTSUM_HALT319_288             (0x1 << DMI_HALTSUM_HALT319_288_OFFSET)
 742 #define DMI_HALTSUM_HALT287_256_OFFSET      8
 743 #define DMI_HALTSUM_HALT287_256_LENGTH      1
 744 #define DMI_HALTSUM_HALT287_256             (0x1 << DMI_HALTSUM_HALT287_256_OFFSET)
 745 #define DMI_HALTSUM_HALT255_224_OFFSET      7
 746 #define DMI_HALTSUM_HALT255_224_LENGTH      1
 747 #define DMI_HALTSUM_HALT255_224             (0x1 << DMI_HALTSUM_HALT255_224_OFFSET)
 748 #define DMI_HALTSUM_HALT223_192_OFFSET      6
 749 #define DMI_HALTSUM_HALT223_192_LENGTH      1
 750 #define DMI_HALTSUM_HALT223_192             (0x1 << DMI_HALTSUM_HALT223_192_OFFSET)
 751 #define DMI_HALTSUM_HALT191_160_OFFSET      5
 752 #define DMI_HALTSUM_HALT191_160_LENGTH      1
 753 #define DMI_HALTSUM_HALT191_160             (0x1 << DMI_HALTSUM_HALT191_160_OFFSET)
 754 #define DMI_HALTSUM_HALT159_128_OFFSET      4
 755 #define DMI_HALTSUM_HALT159_128_LENGTH      1
 756 #define DMI_HALTSUM_HALT159_128             (0x1 << DMI_HALTSUM_HALT159_128_OFFSET)
 757 #define DMI_HALTSUM_HALT127_96_OFFSET       3
 758 #define DMI_HALTSUM_HALT127_96_LENGTH       1
 759 #define DMI_HALTSUM_HALT127_96              (0x1 << DMI_HALTSUM_HALT127_96_OFFSET)
 760 #define DMI_HALTSUM_HALT95_64_OFFSET        2
 761 #define DMI_HALTSUM_HALT95_64_LENGTH        1
 762 #define DMI_HALTSUM_HALT95_64               (0x1 << DMI_HALTSUM_HALT95_64_OFFSET)
 763 #define DMI_HALTSUM_HALT63_32_OFFSET        1
 764 #define DMI_HALTSUM_HALT63_32_LENGTH        1
 765 #define DMI_HALTSUM_HALT63_32               (0x1 << DMI_HALTSUM_HALT63_32_OFFSET)
 766 #define DMI_HALTSUM_HALT31_0_OFFSET         0
 767 #define DMI_HALTSUM_HALT31_0_LENGTH         1
 768 #define DMI_HALTSUM_HALT31_0                (0x1 << DMI_HALTSUM_HALT31_0_OFFSET)
 769 #define DMI_SBCS                            0x03
 770 /*
 771 * When a 1 is written here, triggers a read at the address in {\tt
 772 * sbaddress} using the access size set by \Fsbaccess.
 773  */
 774 #define DMI_SBCS_SBSINGLEREAD_OFFSET        20
 775 #define DMI_SBCS_SBSINGLEREAD_LENGTH        1
 776 #define DMI_SBCS_SBSINGLEREAD               (0x1 << DMI_SBCS_SBSINGLEREAD_OFFSET)
 777 /*
 778 * Select the access size to use for system bus accesses triggered by
 779 * writes to the {\tt sbaddress} registers or \Rsbdatazero.
 780 *
 781 * 0: 8-bit
 782 *
 783 * 1: 16-bit
 784 *
 785 * 2: 32-bit
 786 *
 787 * 3: 64-bit
 788 *
 789 * 4: 128-bit
 790 *
 791 * If an unsupported system bus access size is written here,
 792 * the DM may not
 793 * perform the access, or may perform the access with any access size
 794  */
 795 #define DMI_SBCS_SBACCESS_OFFSET            17
 796 #define DMI_SBCS_SBACCESS_LENGTH            3
 797 #define DMI_SBCS_SBACCESS                   (0x7 << DMI_SBCS_SBACCESS_OFFSET)
 798 /*
 799 * When 1, the internal address value (used by the system bus master)
 800 * is incremented by the access size (in bytes) selected in \Fsbaccess
 801 * after every system bus access.
 802  */
 803 #define DMI_SBCS_SBAUTOINCREMENT_OFFSET     16
 804 #define DMI_SBCS_SBAUTOINCREMENT_LENGTH     1
 805 #define DMI_SBCS_SBAUTOINCREMENT            (0x1 << DMI_SBCS_SBAUTOINCREMENT_OFFSET)
 806 /*
 807 * When 1, every read from \Rsbdatazero automatically triggers a system
 808 * bus read at the new address.
 809  */
 810 #define DMI_SBCS_SBAUTOREAD_OFFSET          15
 811 #define DMI_SBCS_SBAUTOREAD_LENGTH          1
 812 #define DMI_SBCS_SBAUTOREAD                 (0x1 << DMI_SBCS_SBAUTOREAD_OFFSET)
 813 /*
 814 * When the debug module's system bus
 815 * master causes a bus error, this field gets set.
 816 * It remains set until 0 is written to any bit in this field. Until
 817 * that happens, the system bus master is busy and no more accesses can be
 818 * initiated by the debug module.
 819 *
 820 * 0: There was no bus error.
 821 *
 822 * 1: There was a timeout.
 823 *
 824 * 2: A bad address was accessed.
 825 *
 826 * 3: There was some other error (eg. alignment).
 827 *
 828 * 4: The system bus master was busy when a one of the
 829 * {\tt sbaddress} or {\tt sbdata} registers was written,
 830 * or the {\tt sbdata} register was read when it had
 831 * stale data.
 832  */
 833 #define DMI_SBCS_SBERROR_OFFSET             12
 834 #define DMI_SBCS_SBERROR_LENGTH             3
 835 #define DMI_SBCS_SBERROR                    (0x7 << DMI_SBCS_SBERROR_OFFSET)
 836 /*
 837 * Width of system bus addresses in bits. (0 indicates there is no bus
 838 * access support.)
 839  */
 840 #define DMI_SBCS_SBASIZE_OFFSET             5
 841 #define DMI_SBCS_SBASIZE_LENGTH             7
 842 #define DMI_SBCS_SBASIZE                    (0x7f << DMI_SBCS_SBASIZE_OFFSET)
 843 /*
 844 * 1 when 128-bit system bus accesses are supported.
 845  */
 846 #define DMI_SBCS_SBACCESS128_OFFSET         4
 847 #define DMI_SBCS_SBACCESS128_LENGTH         1
 848 #define DMI_SBCS_SBACCESS128                (0x1 << DMI_SBCS_SBACCESS128_OFFSET)
 849 /*
 850 * 1 when 64-bit system bus accesses are supported.
 851  */
 852 #define DMI_SBCS_SBACCESS64_OFFSET          3
 853 #define DMI_SBCS_SBACCESS64_LENGTH          1
 854 #define DMI_SBCS_SBACCESS64                 (0x1 << DMI_SBCS_SBACCESS64_OFFSET)
 855 /*
 856 * 1 when 32-bit system bus accesses are supported.
 857  */
 858 #define DMI_SBCS_SBACCESS32_OFFSET          2
 859 #define DMI_SBCS_SBACCESS32_LENGTH          1
 860 #define DMI_SBCS_SBACCESS32                 (0x1 << DMI_SBCS_SBACCESS32_OFFSET)
 861 /*
 862 * 1 when 16-bit system bus accesses are supported.
 863  */
 864 #define DMI_SBCS_SBACCESS16_OFFSET          1
 865 #define DMI_SBCS_SBACCESS16_LENGTH          1
 866 #define DMI_SBCS_SBACCESS16                 (0x1 << DMI_SBCS_SBACCESS16_OFFSET)
 867 /*
 868 * 1 when 8-bit system bus accesses are supported.
 869  */
 870 #define DMI_SBCS_SBACCESS8_OFFSET           0
 871 #define DMI_SBCS_SBACCESS8_LENGTH           1
 872 #define DMI_SBCS_SBACCESS8                  (0x1 << DMI_SBCS_SBACCESS8_OFFSET)
 873 #define DMI_SBADDRESS0                      0x04
 874 /*
 875 * Accesses bits 31:0 of the internal address.
 876  */
 877 #define DMI_SBADDRESS0_ADDRESS_OFFSET       0
 878 #define DMI_SBADDRESS0_ADDRESS_LENGTH       32
 879 #define DMI_SBADDRESS0_ADDRESS              (0xffffffff << DMI_SBADDRESS0_ADDRESS_OFFSET)
 880 #define DMI_SBADDRESS1                      0x05
 881 /*
 882 * Accesses bits 63:32 of the internal address (if the system address
 883 * bus is that wide).
 884  */
 885 #define DMI_SBADDRESS1_ADDRESS_OFFSET       0
 886 #define DMI_SBADDRESS1_ADDRESS_LENGTH       32
 887 #define DMI_SBADDRESS1_ADDRESS              (0xffffffff << DMI_SBADDRESS1_ADDRESS_OFFSET)
 888 #define DMI_SBADDRESS2                      0x06
 889 /*
 890 * Accesses bits 95:64 of the internal address (if the system address
 891 * bus is that wide).
 892  */
 893 #define DMI_SBADDRESS2_ADDRESS_OFFSET       0
 894 #define DMI_SBADDRESS2_ADDRESS_LENGTH       32
 895 #define DMI_SBADDRESS2_ADDRESS              (0xffffffff << DMI_SBADDRESS2_ADDRESS_OFFSET)
 896 #define DMI_SBDATA0                         0x07
 897 /*
 898 * Accesses bits 31:0 of the internal data.
 899  */
 900 #define DMI_SBDATA0_DATA_OFFSET             0
 901 #define DMI_SBDATA0_DATA_LENGTH             32
 902 #define DMI_SBDATA0_DATA                    (0xffffffff << DMI_SBDATA0_DATA_OFFSET)
 903 #define DMI_SBDATA1                         0x08
 904 /*
 905 * Accesses bits 63:32 of the internal data (if the system bus is
 906 * that wide).
 907  */
 908 #define DMI_SBDATA1_DATA_OFFSET             0
 909 #define DMI_SBDATA1_DATA_LENGTH             32
 910 #define DMI_SBDATA1_DATA                    (0xffffffff << DMI_SBDATA1_DATA_OFFSET)
 911 #define DMI_SBDATA2                         0x09
 912 /*
 913 * Accesses bits 95:64 of the internal data (if the system bus is
 914 * that wide).
 915  */
 916 #define DMI_SBDATA2_DATA_OFFSET             0
 917 #define DMI_SBDATA2_DATA_LENGTH             32
 918 #define DMI_SBDATA2_DATA                    (0xffffffff << DMI_SBDATA2_DATA_OFFSET)
 919 #define DMI_SBDATA3                         0x0a
 920 /*
 921 * Accesses bits 127:96 of the internal data (if the system bus is
 922 * that wide).
 923  */
 924 #define DMI_SBDATA3_DATA_OFFSET             0
 925 #define DMI_SBDATA3_DATA_LENGTH             32
 926 #define DMI_SBDATA3_DATA                    (0xffffffff << DMI_SBDATA3_DATA_OFFSET)
 927 #define DMI_AUTHDATA                        0x0b
 928 #define DMI_AUTHDATA_DATA_OFFSET            0
 929 #define DMI_AUTHDATA_DATA_LENGTH            32
 930 #define DMI_AUTHDATA_DATA                   (0xffffffff << DMI_AUTHDATA_DATA_OFFSET)
 931 #define DMI_ABSTRACTCS                      0x0e
 932 #define DMI_ABSTRACTCS_AUTOEXEC7_OFFSET     15
 933 #define DMI_ABSTRACTCS_AUTOEXEC7_LENGTH     1
 934 #define DMI_ABSTRACTCS_AUTOEXEC7            (0x1 << DMI_ABSTRACTCS_AUTOEXEC7_OFFSET)
 935 #define DMI_ABSTRACTCS_AUTOEXEC6_OFFSET     14
 936 #define DMI_ABSTRACTCS_AUTOEXEC6_LENGTH     1
 937 #define DMI_ABSTRACTCS_AUTOEXEC6            (0x1 << DMI_ABSTRACTCS_AUTOEXEC6_OFFSET)
 938 #define DMI_ABSTRACTCS_AUTOEXEC5_OFFSET     13
 939 #define DMI_ABSTRACTCS_AUTOEXEC5_LENGTH     1
 940 #define DMI_ABSTRACTCS_AUTOEXEC5            (0x1 << DMI_ABSTRACTCS_AUTOEXEC5_OFFSET)
 941 #define DMI_ABSTRACTCS_AUTOEXEC4_OFFSET     12
 942 #define DMI_ABSTRACTCS_AUTOEXEC4_LENGTH     1
 943 #define DMI_ABSTRACTCS_AUTOEXEC4            (0x1 << DMI_ABSTRACTCS_AUTOEXEC4_OFFSET)
 944 #define DMI_ABSTRACTCS_AUTOEXEC3_OFFSET     11
 945 #define DMI_ABSTRACTCS_AUTOEXEC3_LENGTH     1
 946 #define DMI_ABSTRACTCS_AUTOEXEC3            (0x1 << DMI_ABSTRACTCS_AUTOEXEC3_OFFSET)
 947 #define DMI_ABSTRACTCS_AUTOEXEC2_OFFSET     10
 948 #define DMI_ABSTRACTCS_AUTOEXEC2_LENGTH     1
 949 #define DMI_ABSTRACTCS_AUTOEXEC2            (0x1 << DMI_ABSTRACTCS_AUTOEXEC2_OFFSET)
 950 #define DMI_ABSTRACTCS_AUTOEXEC1_OFFSET     9
 951 #define DMI_ABSTRACTCS_AUTOEXEC1_LENGTH     1
 952 #define DMI_ABSTRACTCS_AUTOEXEC1            (0x1 << DMI_ABSTRACTCS_AUTOEXEC1_OFFSET)
 953 /*
 954 * When 1, accesses to \Rdatazero cause the command in \Rcommand to be
 955 * executed again.
 956 *
 957 * The same is true for other other autoexec bits: When 1, accesses to
 958 * {\tt data}N cause the command in \Rcommand to be executed again.
 959  */
 960 #define DMI_ABSTRACTCS_AUTOEXEC0_OFFSET     8
 961 #define DMI_ABSTRACTCS_AUTOEXEC0_LENGTH     1
 962 #define DMI_ABSTRACTCS_AUTOEXEC0            (0x1 << DMI_ABSTRACTCS_AUTOEXEC0_OFFSET)
 963 /*
 964 * Gets set if an abstract command fails. No abstract command is
 965 * started until the value is reset to 0.
 966 *
 967 * 0 (none): No error.
 968 *
 969 * 1 (busy): An abstract command was executing while \Rcommand or one
 970 * of the {\tt data} registers was accessed.
 971 *
 972 * 2 (not supported): The requested command is not supported. A
 973 * command that is not supported while the hart is running may be
 974 * supported when it is halted.
 975 *
 976 * 3 (exception): An exception occurred while executing the command
 977 * (eg. while executing the Program Buffer).
 978 *
 979 * 4 (halt/resume): An abstract command couldn't execute because the
 980 * hart wasn't in the expected state (running/halted).
 981 *
 982 * 7 (other): The command failed for another reason.
 983  */
 984 #define DMI_ABSTRACTCS_CMDERR_OFFSET        5
 985 #define DMI_ABSTRACTCS_CMDERR_LENGTH        3
 986 #define DMI_ABSTRACTCS_CMDERR               (0x7 << DMI_ABSTRACTCS_CMDERR_OFFSET)
 987 /*
 988 * 1: An abstract command is currently being executed.
 989 *
 990 * This bit is set as soon as \Rcommand is written, and isn't cleared
 991 * until that command has completed.
 992  */
 993 #define DMI_ABSTRACTCS_BUSY_OFFSET          4
 994 #define DMI_ABSTRACTCS_BUSY_LENGTH          1
 995 #define DMI_ABSTRACTCS_BUSY                 (0x1 << DMI_ABSTRACTCS_BUSY_OFFSET)
 996 /*
 997 * Number of {\tt data} registers that are implemented as part of the
 998 * abstract command interface. If it's 0 then no abstract interface is
 999 * implemented at all.
1000  */
1001 #define DMI_ABSTRACTCS_DATACOUNT_OFFSET     0
1002 #define DMI_ABSTRACTCS_DATACOUNT_LENGTH     4
1003 #define DMI_ABSTRACTCS_DATACOUNT            (0xf << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
1004 #define DMI_COMMAND                         0x0f
1005 /*
1006 * The type determines the overall functionality of this
1007 * abstract command.
1008  */
1009 #define DMI_COMMAND_TYPE_OFFSET             24
1010 #define DMI_COMMAND_TYPE_LENGTH             8
1011 #define DMI_COMMAND_TYPE                    (0xff << DMI_COMMAND_TYPE_OFFSET)
1012 /*
1013 * This field is interpreted in a command-specific manner,
1014 * described for each abstract command.
1015  */
1016 #define DMI_COMMAND_CONTROL_OFFSET          0
1017 #define DMI_COMMAND_CONTROL_LENGTH          24
1018 #define DMI_COMMAND_CONTROL                 (0xffffff << DMI_COMMAND_CONTROL_OFFSET)
1019 #define DMI_DATA0                           0x10
1020 #define DMI_DATA0_DATA_OFFSET               0
1021 #define DMI_DATA0_DATA_LENGTH               32
1022 #define DMI_DATA0_DATA                      (0xffffffff << DMI_DATA0_DATA_OFFSET)
1023 #define DMI_DATA1                           0x11
1024 #define DMI_DATA2                           0x12
1025 #define DMI_DATA3                           0x13
1026 #define DMI_DATA4                           0x14
1027 #define DMI_DATA5                           0x15
1028 #define DMI_DATA6                           0x16
1029 #define DMI_DATA7                           0x17
1030 #define DMI_DATA8                           0x18
1031 #define DMI_DATA9                           0x19
1032 #define DMI_DATA10                          0x1a
1033 #define DMI_DATA11                          0x1b
1034 #define DMI_SERDATA                         0x1c
1035 #define DMI_SERDATA_DATA_OFFSET             0
1036 #define DMI_SERDATA_DATA_LENGTH             32
1037 #define DMI_SERDATA_DATA                    (0xffffffff << DMI_SERDATA_DATA_OFFSET)
1038 #define DMI_SERCS                           0x1d
1039 /*
1040 * Number of supported serial ports.
1041  */
1042 #define DMI_SERCS_SERIALCOUNT_OFFSET        28
1043 #define DMI_SERCS_SERIALCOUNT_LENGTH        4
1044 #define DMI_SERCS_SERIALCOUNT               (0xf << DMI_SERCS_SERIALCOUNT_OFFSET)
1045 /*
1046 * Select which serial port is accessed by \Rserdata.
1047  */
1048 #define DMI_SERCS_SERIAL_OFFSET             16
1049 #define DMI_SERCS_SERIAL_LENGTH             3
1050 #define DMI_SERCS_SERIAL                    (0x7 << DMI_SERCS_SERIAL_OFFSET)
1051 #define DMI_SERCS_VALID7_OFFSET             15
1052 #define DMI_SERCS_VALID7_LENGTH             1
1053 #define DMI_SERCS_VALID7                    (0x1 << DMI_SERCS_VALID7_OFFSET)
1054 #define DMI_SERCS_FULL_OVERFLOW7_OFFSET     14
1055 #define DMI_SERCS_FULL_OVERFLOW7_LENGTH     1
1056 #define DMI_SERCS_FULL_OVERFLOW7            (0x1 << DMI_SERCS_FULL_OVERFLOW7_OFFSET)
1057 #define DMI_SERCS_VALID6_OFFSET             13
1058 #define DMI_SERCS_VALID6_LENGTH             1
1059 #define DMI_SERCS_VALID6                    (0x1 << DMI_SERCS_VALID6_OFFSET)
1060 #define DMI_SERCS_FULL_OVERFLOW6_OFFSET     12
1061 #define DMI_SERCS_FULL_OVERFLOW6_LENGTH     1
1062 #define DMI_SERCS_FULL_OVERFLOW6            (0x1 << DMI_SERCS_FULL_OVERFLOW6_OFFSET)
1063 #define DMI_SERCS_VALID5_OFFSET             11
1064 #define DMI_SERCS_VALID5_LENGTH             1
1065 #define DMI_SERCS_VALID5                    (0x1 << DMI_SERCS_VALID5_OFFSET)
1066 #define DMI_SERCS_FULL_OVERFLOW5_OFFSET     10
1067 #define DMI_SERCS_FULL_OVERFLOW5_LENGTH     1
1068 #define DMI_SERCS_FULL_OVERFLOW5            (0x1 << DMI_SERCS_FULL_OVERFLOW5_OFFSET)
1069 #define DMI_SERCS_VALID4_OFFSET             9
1070 #define DMI_SERCS_VALID4_LENGTH             1
1071 #define DMI_SERCS_VALID4                    (0x1 << DMI_SERCS_VALID4_OFFSET)
1072 #define DMI_SERCS_FULL_OVERFLOW4_OFFSET     8
1073 #define DMI_SERCS_FULL_OVERFLOW4_LENGTH     1
1074 #define DMI_SERCS_FULL_OVERFLOW4            (0x1 << DMI_SERCS_FULL_OVERFLOW4_OFFSET)
1075 #define DMI_SERCS_VALID3_OFFSET             7
1076 #define DMI_SERCS_VALID3_LENGTH             1
1077 #define DMI_SERCS_VALID3                    (0x1 << DMI_SERCS_VALID3_OFFSET)
1078 #define DMI_SERCS_FULL_OVERFLOW3_OFFSET     6
1079 #define DMI_SERCS_FULL_OVERFLOW3_LENGTH     1
1080 #define DMI_SERCS_FULL_OVERFLOW3            (0x1 << DMI_SERCS_FULL_OVERFLOW3_OFFSET)
1081 #define DMI_SERCS_VALID2_OFFSET             5
1082 #define DMI_SERCS_VALID2_LENGTH             1
1083 #define DMI_SERCS_VALID2                    (0x1 << DMI_SERCS_VALID2_OFFSET)
1084 #define DMI_SERCS_FULL_OVERFLOW2_OFFSET     4
1085 #define DMI_SERCS_FULL_OVERFLOW2_LENGTH     1
1086 #define DMI_SERCS_FULL_OVERFLOW2            (0x1 << DMI_SERCS_FULL_OVERFLOW2_OFFSET)
1087 #define DMI_SERCS_VALID1_OFFSET             3
1088 #define DMI_SERCS_VALID1_LENGTH             1
1089 #define DMI_SERCS_VALID1                    (0x1 << DMI_SERCS_VALID1_OFFSET)
1090 #define DMI_SERCS_FULL_OVERFLOW1_OFFSET     2
1091 #define DMI_SERCS_FULL_OVERFLOW1_LENGTH     1
1092 #define DMI_SERCS_FULL_OVERFLOW1            (0x1 << DMI_SERCS_FULL_OVERFLOW1_OFFSET)
1093 /*
1094 * 1 when the core-to-debugger queue for serial port 0 is not empty.
1095  */
1096 #define DMI_SERCS_VALID0_OFFSET             1
1097 #define DMI_SERCS_VALID0_LENGTH             1
1098 #define DMI_SERCS_VALID0                    (0x1 << DMI_SERCS_VALID0_OFFSET)
1099 /*
1100 * 1 when the debugger-to-core queue for serial port 0 is either full,
1101 * or has overflowed. Overflow state is sticky, and can be reset by
1102 * writing 0 to this bit.
1103  */
1104 #define DMI_SERCS_FULL_OVERFLOW0_OFFSET     0
1105 #define DMI_SERCS_FULL_OVERFLOW0_LENGTH     1
1106 #define DMI_SERCS_FULL_OVERFLOW0            (0x1 << DMI_SERCS_FULL_OVERFLOW0_OFFSET)
1107 #define DMI_PROGBUFCS                       0x1f
1108 /*
1109 * Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 12.
1110 *
1111 * A debugger must not access any Program Buffer locations that
1112 * fall outside the range specified here.
1113 *
1114 * TODO: Explain what can be done with each size of the buffer, to suggest
1115 * why you would want more or less words.
1116  */
1117 #define DMI_PROGBUFCS_PROGSIZE_OFFSET       0
1118 #define DMI_PROGBUFCS_PROGSIZE_LENGTH       4
1119 #define DMI_PROGBUFCS_PROGSIZE              (0xf << DMI_PROGBUFCS_PROGSIZE_OFFSET)
1120 #define DMI_PROGBUF0                        0x20
1121 #define DMI_PROGBUF0_DATA_OFFSET            0
1122 #define DMI_PROGBUF0_DATA_LENGTH            32
1123 #define DMI_PROGBUF0_DATA                   (0xffffffff << DMI_PROGBUF0_DATA_OFFSET)
1124 #define DMI_PROGBUF1                        0x21
1125 #define DMI_PROGBUF2                        0x22
1126 #define DMI_PROGBUF3                        0x23
1127 #define DMI_PROGBUF4                        0x24
1128 #define DMI_PROGBUF5                        0x25
1129 #define DMI_PROGBUF6                        0x26
1130 #define DMI_PROGBUF7                        0x27
1131 #define DMI_PROGBUF8                        0x28
1132 #define DMI_PROGBUF9                        0x29
1133 #define DMI_PROGBUF10                       0x2a
1134 #define DMI_PROGBUF11                       0x2b
1135 #define SERINFO                             0x110
1136 /*
1137 * Like \Fserialzero.
1138  */
1139 #define SERINFO_SERIAL7_OFFSET              7
1140 #define SERINFO_SERIAL7_LENGTH              1
1141 #define SERINFO_SERIAL7                     (0x1 << SERINFO_SERIAL7_OFFSET)
1142 /*
1143 * Like \Fserialzero.
1144  */
1145 #define SERINFO_SERIAL6_OFFSET              6
1146 #define SERINFO_SERIAL6_LENGTH              1
1147 #define SERINFO_SERIAL6                     (0x1 << SERINFO_SERIAL6_OFFSET)
1148 /*
1149 * Like \Fserialzero.
1150  */
1151 #define SERINFO_SERIAL5_OFFSET              5
1152 #define SERINFO_SERIAL5_LENGTH              1
1153 #define SERINFO_SERIAL5                     (0x1 << SERINFO_SERIAL5_OFFSET)
1154 /*
1155 * Like \Fserialzero.
1156  */
1157 #define SERINFO_SERIAL4_OFFSET              4
1158 #define SERINFO_SERIAL4_LENGTH              1
1159 #define SERINFO_SERIAL4                     (0x1 << SERINFO_SERIAL4_OFFSET)
1160 /*
1161 * Like \Fserialzero.
1162  */
1163 #define SERINFO_SERIAL3_OFFSET              3
1164 #define SERINFO_SERIAL3_LENGTH              1
1165 #define SERINFO_SERIAL3                     (0x1 << SERINFO_SERIAL3_OFFSET)
1166 /*
1167 * Like \Fserialzero.
1168  */
1169 #define SERINFO_SERIAL2_OFFSET              2
1170 #define SERINFO_SERIAL2_LENGTH              1
1171 #define SERINFO_SERIAL2                     (0x1 << SERINFO_SERIAL2_OFFSET)
1172 /*
1173 * Like \Fserialzero.
1174  */
1175 #define SERINFO_SERIAL1_OFFSET              1
1176 #define SERINFO_SERIAL1_LENGTH              1
1177 #define SERINFO_SERIAL1                     (0x1 << SERINFO_SERIAL1_OFFSET)
1178 /*
1179 * 1 means serial interface 0 is supported.
1180  */
1181 #define SERINFO_SERIAL0_OFFSET              0
1182 #define SERINFO_SERIAL0_LENGTH              1
1183 #define SERINFO_SERIAL0                     (0x1 << SERINFO_SERIAL0_OFFSET)
1184 #define SERSEND0                            0x200
1185 #define SERRECV0                            0x204
1186 #define SERSTAT0                            0x208
1187 /*
1188 * Send ready. 1 when the core-to-debugger queue is not full. 0
1189 * otherwise.
1190  */
1191 #define SERSTAT0_SENDR_OFFSET               1
1192 #define SERSTAT0_SENDR_LENGTH               1
1193 #define SERSTAT0_SENDR                      (0x1 << SERSTAT0_SENDR_OFFSET)
1194 /*
1195 * Receive ready. 1 when the debugger-to-core queue is not empty. 0
1196 * otherwise.
1197  */
1198 #define SERSTAT0_RECVR_OFFSET               0
1199 #define SERSTAT0_RECVR_LENGTH               1
1200 #define SERSTAT0_RECVR                      (0x1 << SERSTAT0_RECVR_OFFSET)
1201 #define SERSEND1                            0x20c
1202 #define SERRECV1                            0x210
1203 #define SERSTAT1                            0x214
1204 #define SERSEND2                            0x218
1205 #define SERRECV2                            0x21c
1206 #define SERSTAT2                            0x220
1207 #define SERSEND3                            0x224
1208 #define SERRECV3                            0x228
1209 #define SERSTAT3                            0x22c
1210 #define SERSEND4                            0x230
1211 #define SERRECV4                            0x234
1212 #define SERSTAT4                            0x238
1213 #define SERSEND5                            0x23c
1214 #define SERRECV5                            0x240
1215 #define SERSTAT5                            0x244
1216 #define SERSEND6                            0x248
1217 #define SERRECV6                            0x24c
1218 #define SERSTAT6                            0x250
1219 #define SERSEND7                            0x254
1220 #define SERRECV7                            0x258
1221 #define SERSTAT7                            0x25c
1222 #define TRACE                               0x728
1223 /*
1224 * 1 if the trace buffer has wrapped since the last time \Fdiscard was
1225 * written. 0 otherwise.
1226  */
1227 #define TRACE_WRAPPED_OFFSET                24
1228 #define TRACE_WRAPPED_LENGTH                1
1229 #define TRACE_WRAPPED                       (0x1 << TRACE_WRAPPED_OFFSET)
1230 /*
1231 * Emit Timestamp trace sequences.
1232  */
1233 #define TRACE_EMITTIMESTAMP_OFFSET          23
1234 #define TRACE_EMITTIMESTAMP_LENGTH          1
1235 #define TRACE_EMITTIMESTAMP                 (0x1 << TRACE_EMITTIMESTAMP_OFFSET)
1236 /*
1237 * Emit Store Data trace sequences.
1238  */
1239 #define TRACE_EMITSTOREDATA_OFFSET          22
1240 #define TRACE_EMITSTOREDATA_LENGTH          1
1241 #define TRACE_EMITSTOREDATA                 (0x1 << TRACE_EMITSTOREDATA_OFFSET)
1242 /*
1243 * Emit Load Data trace sequences.
1244  */
1245 #define TRACE_EMITLOADDATA_OFFSET           21
1246 #define TRACE_EMITLOADDATA_LENGTH           1
1247 #define TRACE_EMITLOADDATA                  (0x1 << TRACE_EMITLOADDATA_OFFSET)
1248 /*
1249 * Emit Store Address trace sequences.
1250  */
1251 #define TRACE_EMITSTOREADDR_OFFSET          20
1252 #define TRACE_EMITSTOREADDR_LENGTH          1
1253 #define TRACE_EMITSTOREADDR                 (0x1 << TRACE_EMITSTOREADDR_OFFSET)
1254 /*
1255 * Emit Load Address trace sequences.
1256  */
1257 #define TRACE_EMITLOADADDR_OFFSET           19
1258 #define TRACE_EMITLOADADDR_LENGTH           1
1259 #define TRACE_EMITLOADADDR                  (0x1 << TRACE_EMITLOADADDR_OFFSET)
1260 /*
1261 * Emit Privilege Level trace sequences.
1262  */
1263 #define TRACE_EMITPRIV_OFFSET               18
1264 #define TRACE_EMITPRIV_LENGTH               1
1265 #define TRACE_EMITPRIV                      (0x1 << TRACE_EMITPRIV_OFFSET)
1266 /*
1267 * Emit Branch Taken and Branch Not Taken trace sequences.
1268  */
1269 #define TRACE_EMITBRANCH_OFFSET             17
1270 #define TRACE_EMITBRANCH_LENGTH             1
1271 #define TRACE_EMITBRANCH                    (0x1 << TRACE_EMITBRANCH_OFFSET)
1272 /*
1273 * Emit PC trace sequences.
1274  */
1275 #define TRACE_EMITPC_OFFSET                 16
1276 #define TRACE_EMITPC_LENGTH                 1
1277 #define TRACE_EMITPC                        (0x1 << TRACE_EMITPC_OFFSET)
1278 /*
1279 * Determine what happens when the trace buffer is full.  0 means wrap
1280 * and overwrite. 1 means turn off trace until \Fdiscard is written as 1.
1281 * 2 means cause a trace full exception. 3 is reserved for future use.
1282  */
1283 #define TRACE_FULLACTION_OFFSET             8
1284 #define TRACE_FULLACTION_LENGTH             2
1285 #define TRACE_FULLACTION                    (0x3 << TRACE_FULLACTION_OFFSET)
1286 /*
1287 * 0: Trace to a dedicated on-core RAM (which is not further defined in
1288 * this spec).
1289 *
1290 * 1: Trace to RAM on the system bus.
1291 *
1292 * 2: Send trace data to a dedicated off-chip interface (which is not
1293 * defined in this spec). This does not affect execution speed.
1294 *
1295 * 3: Reserved for future use.
1296 *
1297 * Options 0 and 1 slow down execution (eg. because of system bus
1298 * contention).
1299  */
1300 #define TRACE_DESTINATION_OFFSET            4
1301 #define TRACE_DESTINATION_LENGTH            2
1302 #define TRACE_DESTINATION                   (0x3 << TRACE_DESTINATION_OFFSET)
1303 /*
1304 * When 1, the trace logic may stall processor execution to ensure it
1305 * can emit all the trace sequences required. When 0 individual trace
1306 * sequences may be dropped.
1307  */
1308 #define TRACE_STALL_OFFSET                  2
1309 #define TRACE_STALL_LENGTH                  1
1310 #define TRACE_STALL                         (0x1 << TRACE_STALL_OFFSET)
1311 /*
1312 * Writing 1 to this bit tells the trace logic that any trace
1313 * collected is no longer required. When tracing to RAM, it resets the
1314 * trace write pointer to the start of the memory, as well as
1315 * \Fwrapped.
1316  */
1317 #define TRACE_DISCARD_OFFSET                1
1318 #define TRACE_DISCARD_LENGTH                1
1319 #define TRACE_DISCARD                       (0x1 << TRACE_DISCARD_OFFSET)
1320 #define TRACE_SUPPORTED_OFFSET              0
1321 #define TRACE_SUPPORTED_LENGTH              1
1322 #define TRACE_SUPPORTED                     (0x1 << TRACE_SUPPORTED_OFFSET)
1323 #define TBUFSTART                           0x729
1324 #define TBUFEND                             0x72a
1325 #define TBUFWRITE                           0x72b
1326 #define SHORTNAME                           0x123
1327 /*
1328 * Description of what this field is used for.
1329  */
1330 #define SHORTNAME_FIELD_OFFSET              0
1331 #define SHORTNAME_FIELD_LENGTH              8
1332 #define SHORTNAME_FIELD                     (0xff << SHORTNAME_FIELD_OFFSET)
1333 #define AC_ACCESS_REGISTER                  None
1334 /*
1335 * This is 0 to indicate Access Register Command.
1336  */
1337 #define AC_ACCESS_REGISTER_TYPE_OFFSET      24
1338 #define AC_ACCESS_REGISTER_TYPE_LENGTH      8
1339 #define AC_ACCESS_REGISTER_TYPE             (0xff << AC_ACCESS_REGISTER_TYPE_OFFSET)
1340 /*
1341 * 2: Access the lowest 32 bits of the register.
1342 *
1343 * 3: Access the lowest 64 bits of the register.
1344 *
1345 * 4: Access the lowest 128 bits of the register.
1346 *
1347 * If \Fsize specifies a size larger than the register is, then the
1348 * access must fail. If a register is accessible, then \Fsize matching
1349 * the register's actual size must be supported.
1350  */
1351 #define AC_ACCESS_REGISTER_SIZE_OFFSET      19
1352 #define AC_ACCESS_REGISTER_SIZE_LENGTH      3
1353 #define AC_ACCESS_REGISTER_SIZE             (0x7 << AC_ACCESS_REGISTER_SIZE_OFFSET)
1354 /*
1355 * When 1, execute the program in the Program Buffer exactly once
1356 * before performing the read/write.
1357  */
1358 #define AC_ACCESS_REGISTER_PREEXEC_OFFSET   18
1359 #define AC_ACCESS_REGISTER_PREEXEC_LENGTH   1
1360 #define AC_ACCESS_REGISTER_PREEXEC          (0x1 << AC_ACCESS_REGISTER_PREEXEC_OFFSET)
1361 /*
1362 * When 1, execute the program in the Program Buffer exactly once
1363 * after performing the read/write.
1364  */
1365 #define AC_ACCESS_REGISTER_POSTEXEC_OFFSET  17
1366 #define AC_ACCESS_REGISTER_POSTEXEC_LENGTH  1
1367 #define AC_ACCESS_REGISTER_POSTEXEC         (0x1 << AC_ACCESS_REGISTER_POSTEXEC_OFFSET)
1368 /*
1369 * 0: Copy data from the specified register into {\tt arg0} portion
1370 * of {\tt data}.
1371 *
1372 * 1: Copy data from {\tt arg0} portion of {\tt data} into the
1373 * specified register.
1374  */
1375 #define AC_ACCESS_REGISTER_WRITE_OFFSET     16
1376 #define AC_ACCESS_REGISTER_WRITE_LENGTH     1
1377 #define AC_ACCESS_REGISTER_WRITE            (0x1 << AC_ACCESS_REGISTER_WRITE_OFFSET)
1378 /*
1379 * Number of the register to access, as described in Table~\ref{tab:regno}.
1380  */
1381 #define AC_ACCESS_REGISTER_REGNO_OFFSET     0
1382 #define AC_ACCESS_REGISTER_REGNO_LENGTH     16
1383 #define AC_ACCESS_REGISTER_REGNO            (0xffff << AC_ACCESS_REGISTER_REGNO_OFFSET)
1384 #define AC_QUICK_ACCESS                     None
1385 /*
1386 * This is 1 to indicate Quick Access command.
1387  */
1388 #define AC_QUICK_ACCESS_TYPE_OFFSET         24
1389 #define AC_QUICK_ACCESS_TYPE_LENGTH         8
1390 #define AC_QUICK_ACCESS_TYPE                (0xff << AC_QUICK_ACCESS_TYPE_OFFSET)