d0fd2e15acd58855d15f5564bc0ab55d5705b9c3
1 // See LICENSE for license details.
2 #ifndef _RISCV_DEBUG_MODULE_H
3 #define _RISCV_DEBUG_MODULE_H
9 class debug_module_t
: public abstract_device_t
14 bool load(reg_t addr
, size_t len
, uint8_t* bytes
);
15 bool store(reg_t addr
, size_t len
, const uint8_t* bytes
);
17 void ram_write32(unsigned int index
, uint32_t value
);
18 uint32_t ram_read32(unsigned int index
);
20 void set_interrupt(uint32_t hartid
) {
21 interrupt
.insert(hartid
);
23 void clear_interrupt(uint32_t hartid
) {
24 interrupt
.erase(hartid
);
26 bool get_interrupt(uint32_t hartid
) const {
27 return interrupt
.find(hartid
) != interrupt
.end();
30 void set_halt_notification(uint32_t hartid
) {
31 halt_notification
.insert(hartid
);
33 void clear_halt_notification(uint32_t hartid
) {
34 halt_notification
.erase(hartid
);
36 bool get_halt_notification(uint32_t hartid
) const {
37 return halt_notification
.find(hartid
) != halt_notification
.end();
40 // Debug Module Interface that the debugger (in our case through JTAG DTM)
41 // uses to access the DM.
42 // Return true for success, false for failure.
43 bool dmi_read(unsigned address
, uint32_t *value
);
44 bool dmi_write(unsigned address
, uint32_t value
);
47 // Track which interrupts from module to debugger are set.
48 std::set
<uint32_t> interrupt
;
49 // Track which halt notifications from debugger to module are set.
50 std::set
<uint32_t> halt_notification
;
51 char debug_ram
[DEBUG_RAM_SIZE
];