1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #if (-1 != ~0) || ((-1 >> 1) != -1)
7 # error spike requires a two''s-complement c++ implementation
10 #ifdef WORDS_BIGENDIAN
11 # error spike requires a little-endian host
20 #include "softfloat_types.h"
21 #include "specialize.h"
24 typedef int64_t sreg_t
;
25 typedef uint64_t reg_t
;
29 const int NCSR
= 4096;
40 #define FSR_RD_SHIFT 5
41 #define FSR_RD (0x7 << FSR_RD_SHIFT)
49 #define FSR_AEXC_SHIFT 0
50 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
51 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
52 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
53 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
54 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
55 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
57 #define insn_length(x) \
58 (((x) & 0x03) < 0x03 ? 2 : \
59 ((x) & 0x1f) < 0x1f ? 4 : \
60 ((x) & 0x3f) < 0x3f ? 6 : \
62 #define MAX_INSN_LENGTH 8
65 typedef uint64_t insn_bits_t
;
70 insn_t(insn_bits_t bits
) : b(bits
) {}
71 insn_bits_t
bits() { return b
; }
72 int length() { return insn_length(b
); }
73 int64_t i_imm() { return int64_t(b
) >> 20; }
74 int64_t shamt() { return x(20, 6); }
75 int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
76 int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
77 int64_t u_imm() { return int64_t(b
) >> 12 << 12; }
78 int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
79 uint64_t rd() { return x(7, 5); }
80 uint64_t rs1() { return x(15, 5); }
81 uint64_t rs2() { return x(20, 5); }
82 uint64_t rs3() { return x(27, 5); }
83 uint64_t rm() { return x(12, 3); }
84 uint64_t csr() { return x(20, 12); }
86 int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
87 int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); }
88 int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); }
89 int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); }
90 int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
91 int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
92 int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); }
93 int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); }
94 int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); }
95 int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); }
96 int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); }
97 int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); }
98 int64_t rvc_simm3() { return x(10, 3); }
99 uint64_t rvc_rd() { return rd(); }
100 uint64_t rvc_rs1() { return rd(); }
101 uint64_t rvc_rs2() { return x(2, 5); }
102 uint64_t rvc_rs1s() { return 8 + x(7, 3); }
103 uint64_t rvc_rs2s() { return 8 + x(2, 3); }
106 uint64_t x(int lo
, int len
) { return (b
>> lo
) & ((insn_bits_t(1) << len
)-1); }
107 uint64_t xs(int lo
, int len
) { return int64_t(b
) << (64-lo
-len
) >> (64-len
); }
108 uint64_t imm_sign() { return xs(63, 1); }
111 template <class T
, size_t N
, bool zero_reg
>
115 void write(size_t i
, T value
)
117 if (!zero_reg
|| i
!= 0)
120 const T
& operator [] (size_t i
) const
128 // helpful macros, etc
129 #define MMU (*p->get_mmu())
130 #define STATE (*p->get_state())
131 #define READ_REG(reg) STATE.XPR[reg]
132 #define READ_FREG(reg) STATE.FPR[reg]
133 #define RS1 READ_REG(insn.rs1())
134 #define RS2 READ_REG(insn.rs2())
135 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
137 #ifndef RISCV_ENABLE_COMMITLOG
138 # define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
139 # define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value))
141 # define WRITE_REG(reg, value) ({ \
142 reg_t wdata = (value); /* value may have side effects */ \
143 STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \
144 STATE.XPR.write(reg, wdata); \
146 # define WRITE_FREG(reg, value) ({ \
147 freg_t wdata = freg(value); /* value may have side effects */ \
148 STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \
149 DO_WRITE_FREG(reg, wdata); \
154 #define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value)
155 #define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value)
156 #define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value)
157 #define RVC_RS1 READ_REG(insn.rvc_rs1())
158 #define RVC_RS2 READ_REG(insn.rvc_rs2())
159 #define RVC_RS1S READ_REG(insn.rvc_rs1s())
160 #define RVC_RS2S READ_REG(insn.rvc_rs2s())
161 #define RVC_FRS2 READ_FREG(insn.rvc_rs2())
162 #define RVC_FRS2S READ_FREG(insn.rvc_rs2s())
163 #define RVC_SP READ_REG(X_SP)
166 #define FRS1 READ_FREG(insn.rs1())
167 #define FRS2 READ_FREG(insn.rs2())
168 #define FRS3 READ_FREG(insn.rs3())
169 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
170 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
171 #define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state)
172 #define WRITE_FRD(value) WRITE_FREG(insn.rd(), value)
174 #define SHAMT (insn.i_imm() & 0x3F)
175 #define BRANCH_TARGET (pc + insn.sb_imm())
176 #define JUMP_TARGET (pc + insn.uj_imm())
177 #define RM ({ int rm = insn.rm(); \
178 if(rm == 7) rm = STATE.frm; \
179 if(rm > 4) throw trap_illegal_instruction(0); \
182 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
183 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
185 #define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0)
186 #define require_privilege(p) require(STATE.prv >= (p))
187 #define require_rv64 require(xlen == 64)
188 #define require_rv32 require(xlen == 32)
189 #define require_extension(s) require(p->supports_extension(s))
190 #define require_fp require((STATE.mstatus & MSTATUS_FS) != 0)
191 #define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0)
193 #define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \
195 STATE.fflags |= softfloat_exceptionFlags; \
197 softfloat_exceptionFlags = 0; })
199 #define sext32(x) ((sreg_t)(int32_t)(x))
200 #define zext32(x) ((reg_t)(uint32_t)(x))
201 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
202 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
205 do { p->check_pc_alignment(x); \
206 npc = sext_xlen(x); \
209 #define set_pc_and_serialize(x) \
210 do { reg_t __npc = (x) & p->pc_alignment_mask(); \
211 npc = PC_SERIALIZE_AFTER; \
216 do { set_pc_and_serialize(npc); \
217 npc = PC_SERIALIZE_WFI; \
220 #define serialize() set_pc_and_serialize(npc)
222 /* Sentinel PC values to serialize simulator pipeline */
223 #define PC_SERIALIZE_BEFORE 3
224 #define PC_SERIALIZE_AFTER 5
225 #define PC_SERIALIZE_WFI 7
226 #define invalid_pc(pc) ((pc) & 1)
228 /* Convenience wrappers to simplify softfloat code sequences */
229 #define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0))
230 #define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI)
231 #define isBoxedF64(r) ((r.v[1] + 1) == 0)
232 #define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI)
233 typedef float128_t freg_t
;
234 inline float32_t
f32(uint32_t v
) { return { v
}; }
235 inline float64_t
f64(uint64_t v
) { return { v
}; }
236 inline float32_t
f32(freg_t r
) { return f32(unboxF32(r
)); }
237 inline float64_t
f64(freg_t r
) { return f64(unboxF64(r
)); }
238 inline float128_t
f128(freg_t r
) { return r
; }
239 inline freg_t
freg(float32_t f
) { return { ((uint64_t)-1 << 32) | f
.v
, (uint64_t)-1 }; }
240 inline freg_t
freg(float64_t f
) { return { f
.v
, (uint64_t)-1 }; }
241 inline freg_t
freg(float128_t f
) { return f
; }
242 #define F32_SIGN ((uint32_t)1 << 31)
243 #define F64_SIGN ((uint64_t)1 << 63)
244 #define fsgnj32(a, b, n, x) \
245 f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN))
246 #define fsgnj64(a, b, n, x) \
247 f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN))
249 #define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0])
250 inline float128_t
defaultNaNF128()
253 nan
.v
[1] = defaultNaNF128UI64
;
254 nan
.v
[0] = defaultNaNF128UI0
;
257 inline freg_t
fsgnj128(freg_t a
, freg_t b
, bool n
, bool x
)
259 a
.v
[1] = (a
.v
[1] & ~F64_SIGN
) | (((x
? a
.v
[1] : n
? F64_SIGN
: 0) ^ b
.v
[1]) & F64_SIGN
);
262 inline freg_t
f128_negate(freg_t a
)
268 #define validate_csr(which, write) ({ \
269 if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \
270 STATE.serialized = false; \
271 unsigned csr_priv = get_field((which), 0x300); \
272 unsigned csr_read_only = get_field((which), 0xC00) == 3; \
273 if (((write) && csr_read_only) || STATE.prv < csr_priv) \
274 throw trap_illegal_instruction(0); \
277 // Seems that 0x0 doesn't work.
278 #define DEBUG_START 0x100
279 #define DEBUG_END (0x1000 - 1)