31e4068df6a4e46d35dc72e30da3c797abf7c55c
1 // See LICENSE for license details.
10 static const char* xpr
[] = {
11 "zero", "ra", "s0", "s1", "s2", "s3", "s4", "s5",
12 "s6", "s7", "s8", "s9", "s10", "s11", "sp", "tp",
13 "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5",
14 "a6", "a7", "t0", "t1", "t2", "t3", "t4", "gp"
17 static const char* fpr
[] = {
18 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
19 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
20 "fv0", "fv1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
21 "fa6", "fa7", "ft0", "ft1", "ft2", "ft3", "ft4", "ft5"
24 struct : public arg_t
{
25 std::string
to_string(insn_t insn
) const {
26 return std::to_string((int)insn
.i_imm()) + '(' + xpr
[insn
.rs1()] + ')';
30 struct : public arg_t
{
31 std::string
to_string(insn_t insn
) const {
32 return std::to_string((int)insn
.s_imm()) + '(' + xpr
[insn
.rs1()] + ')';
36 struct : public arg_t
{
37 std::string
to_string(insn_t insn
) const {
38 return std::string("0(") + xpr
[insn
.rs1()] + ')';
42 struct : public arg_t
{
43 std::string
to_string(insn_t insn
) const {
44 return xpr
[insn
.rd()];
48 struct : public arg_t
{
49 std::string
to_string(insn_t insn
) const {
50 return xpr
[insn
.rs1()];
54 struct : public arg_t
{
55 std::string
to_string(insn_t insn
) const {
56 return xpr
[insn
.rs2()];
60 struct : public arg_t
{
61 std::string
to_string(insn_t insn
) const {
62 return fpr
[insn
.rd()];
66 struct : public arg_t
{
67 std::string
to_string(insn_t insn
) const {
68 return fpr
[insn
.rs1()];
72 struct : public arg_t
{
73 std::string
to_string(insn_t insn
) const {
74 return fpr
[insn
.rs2()];
78 struct : public arg_t
{
79 std::string
to_string(insn_t insn
) const {
80 return fpr
[insn
.rs3()];
84 struct : public arg_t
{
85 std::string
to_string(insn_t insn
) const {
88 #define DECLARE_CSR(name, num) case num: return #name;
91 default: return "unknown";
96 struct : public arg_t
{
97 std::string
to_string(insn_t insn
) const {
98 return std::to_string((int)insn
.i_imm());
102 struct : public arg_t
{
103 std::string
to_string(insn_t insn
) const {
105 s
<< std::hex
<< "0x" << ((uint32_t)insn
.u_imm() >> 12);
110 struct : public arg_t
{
111 std::string
to_string(insn_t insn
) const {
112 return std::to_string(insn
.rs1());
116 struct : public arg_t
{
117 std::string
to_string(insn_t insn
) const {
119 int32_t target
= insn
.sb_imm();
120 char sign
= target
>= 0 ? '+' : '-';
121 s
<< "pc " << sign
<< ' ' << abs(target
);
126 struct : public arg_t
{
127 std::string
to_string(insn_t insn
) const {
129 int32_t target
= insn
.sb_imm();
130 char sign
= target
>= 0 ? '+' : '-';
131 s
<< "pc " << sign
<< std::hex
<< " 0x" << abs(target
);
136 std::string
disassembler_t::disassemble(insn_t insn
)
138 const disasm_insn_t
* disasm_insn
= lookup(insn
);
139 return disasm_insn
? disasm_insn
->to_string(insn
) : "unknown";
142 disassembler_t::disassembler_t()
144 const uint32_t mask_rd
= 0x1fUL
<< 7;
145 const uint32_t match_rd_ra
= 1UL << 7;
146 const uint32_t mask_rs1
= 0x1fUL
<< 15;
147 const uint32_t match_rs1_ra
= 1UL << 15;
148 const uint32_t mask_rs2
= 0x1fUL
<< 15;
149 const uint32_t mask_imm
= 0xfffUL
<< 20;
151 #define DECLARE_INSN(code, match, mask) \
152 const uint32_t match_##code = match; \
153 const uint32_t mask_##code = mask;
154 #include "encoding.h"
157 // explicit per-instruction disassembly
158 #define DISASM_INSN(name, code, extra, ...) \
159 add_insn(new disasm_insn_t(name, match_##code, mask_##code | (extra), __VA_ARGS__));
160 #define DEFINE_NOARG(code) \
161 add_insn(new disasm_insn_t(#code, match_##code, mask_##code, {}));
162 #define DEFINE_RTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &xrs2})
163 #define DEFINE_ITYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs1, &imm})
164 #define DEFINE_I0TYPE(name, code) DISASM_INSN(name, code, mask_rs1, {&xrd, &imm})
165 #define DEFINE_I1TYPE(name, code) DISASM_INSN(name, code, mask_imm, {&xrd, &xrs1})
166 #define DEFINE_I2TYPE(name, code) DISASM_INSN(name, code, mask_rd | mask_imm, {&xrs1})
167 #define DEFINE_LTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &bigimm})
168 #define DEFINE_BTYPE(code) DISASM_INSN(#code, code, 0, {&xrs1, &xrs2, &branch_target})
169 #define DEFINE_B0TYPE(name, code) DISASM_INSN(name, code, mask_rs1 | mask_rs2, {&branch_target})
170 #define DEFINE_B1TYPE(name, code) DISASM_INSN(name, code, mask_rs2, {&xrs1, &branch_target})
171 #define DEFINE_XLOAD(code) DISASM_INSN(#code, code, 0, {&xrd, &load_address})
172 #define DEFINE_XSTORE(code) DISASM_INSN(#code, code, 0, {&xrs2, &store_address})
173 #define DEFINE_XAMO(code) DISASM_INSN(#code, code, 0, {&xrd, &xrs2, &amo_address})
174 #define DEFINE_FLOAD(code) DISASM_INSN(#code, code, 0, {&frd, &load_address})
175 #define DEFINE_FSTORE(code) DISASM_INSN(#code, code, 0, {&frs2, &store_address})
176 #define DEFINE_FRTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2})
177 #define DEFINE_FR1TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1})
178 #define DEFINE_FR3TYPE(code) DISASM_INSN(#code, code, 0, {&frd, &frs1, &frs2, &frs3})
179 #define DEFINE_FXTYPE(code) DISASM_INSN(#code, code, 0, {&xrd, &frs1})
180 #define DEFINE_XFTYPE(code) DISASM_INSN(#code, code, 0, {&frd, &xrs1})
195 DEFINE_XAMO(amoadd_w
)
196 DEFINE_XAMO(amoswap_w
)
197 DEFINE_XAMO(amoand_w
)
199 DEFINE_XAMO(amoxor_w
)
200 DEFINE_XAMO(amomin_w
)
201 DEFINE_XAMO(amomax_w
)
202 DEFINE_XAMO(amominu_w
)
203 DEFINE_XAMO(amomaxu_w
)
204 DEFINE_XAMO(amoadd_d
)
205 DEFINE_XAMO(amoswap_d
)
206 DEFINE_XAMO(amoand_d
)
208 DEFINE_XAMO(amoxor_d
)
209 DEFINE_XAMO(amomin_d
)
210 DEFINE_XAMO(amomax_d
)
211 DEFINE_XAMO(amominu_d
)
212 DEFINE_XAMO(amomaxu_d
)
225 add_insn(new disasm_insn_t("j", match_jal
, mask_jal
| mask_rd
, {&jump_target
}));
226 add_insn(new disasm_insn_t("jal", match_jal
| match_rd_ra
, mask_jal
| mask_rd
, {&jump_target
}));
227 add_insn(new disasm_insn_t("jal", match_jal
, mask_jal
, {&xrd
, &jump_target
}));
229 DEFINE_B0TYPE("b", beq
);
230 DEFINE_B1TYPE("beqz", beq
);
231 DEFINE_B1TYPE("bnez", bne
);
232 DEFINE_B1TYPE("bltz", blt
);
233 DEFINE_B1TYPE("bgez", bge
);
244 DEFINE_I2TYPE("jr", jalr
);
245 add_insn(new disasm_insn_t("jalr", match_jalr
| match_rd_ra
, mask_jalr
| mask_rd
| mask_imm
, {&xrs1
}));
246 add_insn(new disasm_insn_t("ret", match_jalr
| match_rs1_ra
, mask_jalr
| mask_rd
| mask_rs1
| mask_imm
, {}));
249 add_insn(new disasm_insn_t("nop", match_addi
, mask_addi
| mask_rd
| mask_rs1
| mask_imm
, {}));
250 DEFINE_I0TYPE("li", addi
);
251 DEFINE_I1TYPE("move", addi
);
279 DEFINE_RTYPE(mulhsu
);
296 DEFINE_NOARG(sbreak
);
298 DEFINE_NOARG(fence_i
);
300 add_insn(new disasm_insn_t("csrr", match_csrrs
, mask_csrrs
| mask_rs1
, {&xrd
, &csr
}));
301 add_insn(new disasm_insn_t("csrw", match_csrrw
, mask_csrrw
| mask_rd
, {&csr
, &xrs1
}));
302 add_insn(new disasm_insn_t("csrrw", match_csrrw
, mask_csrrw
, {&xrd
, &csr
, &xrs1
}));
303 add_insn(new disasm_insn_t("csrrs", match_csrrs
, mask_csrrs
, {&xrd
, &csr
, &xrs1
}));
304 add_insn(new disasm_insn_t("csrrc", match_csrrc
, mask_csrrc
, {&xrd
, &csr
, &xrs1
}));
305 add_insn(new disasm_insn_t("csrrwi", match_csrrwi
, mask_csrrwi
, {&xrd
, &csr
, &zimm5
}));
306 add_insn(new disasm_insn_t("csrrsi", match_csrrsi
, mask_csrrsi
, {&xrd
, &csr
, &zimm5
}));
307 add_insn(new disasm_insn_t("csrrci", match_csrrci
, mask_csrrci
, {&xrd
, &csr
, &zimm5
}));
310 DEFINE_FRTYPE(fadd_s
);
311 DEFINE_FRTYPE(fsub_s
);
312 DEFINE_FRTYPE(fmul_s
);
313 DEFINE_FRTYPE(fdiv_s
);
314 DEFINE_FR1TYPE(fsqrt_s
);
315 DEFINE_FRTYPE(fmin_s
);
316 DEFINE_FRTYPE(fmax_s
);
317 DEFINE_FR3TYPE(fmadd_s
);
318 DEFINE_FR3TYPE(fmsub_s
);
319 DEFINE_FR3TYPE(fnmadd_s
);
320 DEFINE_FR3TYPE(fnmsub_s
);
321 DEFINE_FRTYPE(fsgnj_s
);
322 DEFINE_FRTYPE(fsgnjn_s
);
323 DEFINE_FRTYPE(fsgnjx_s
);
324 DEFINE_FR1TYPE(fcvt_s_d
);
325 DEFINE_XFTYPE(fcvt_s_l
);
326 DEFINE_XFTYPE(fcvt_s_lu
);
327 DEFINE_XFTYPE(fcvt_s_w
);
328 DEFINE_XFTYPE(fcvt_s_wu
);
329 DEFINE_XFTYPE(fcvt_s_wu
);
330 DEFINE_XFTYPE(fmv_s_x
);
331 DEFINE_FXTYPE(fcvt_l_s
);
332 DEFINE_FXTYPE(fcvt_lu_s
);
333 DEFINE_FXTYPE(fcvt_w_s
);
334 DEFINE_FXTYPE(fcvt_wu_s
);
335 DEFINE_FXTYPE(fmv_x_s
);
336 DEFINE_FXTYPE(feq_s
);
337 DEFINE_FXTYPE(flt_s
);
338 DEFINE_FXTYPE(fle_s
);
340 DEFINE_FRTYPE(fadd_d
);
341 DEFINE_FRTYPE(fsub_d
);
342 DEFINE_FRTYPE(fmul_d
);
343 DEFINE_FRTYPE(fdiv_d
);
344 DEFINE_FR1TYPE(fsqrt_d
);
345 DEFINE_FRTYPE(fmin_d
);
346 DEFINE_FRTYPE(fmax_d
);
347 DEFINE_FR3TYPE(fmadd_d
);
348 DEFINE_FR3TYPE(fmsub_d
);
349 DEFINE_FR3TYPE(fnmadd_d
);
350 DEFINE_FR3TYPE(fnmsub_d
);
351 DEFINE_FRTYPE(fsgnj_d
);
352 DEFINE_FRTYPE(fsgnjn_d
);
353 DEFINE_FRTYPE(fsgnjx_d
);
354 DEFINE_FR1TYPE(fcvt_d_s
);
355 DEFINE_XFTYPE(fcvt_d_l
);
356 DEFINE_XFTYPE(fcvt_d_lu
);
357 DEFINE_XFTYPE(fcvt_d_w
);
358 DEFINE_XFTYPE(fcvt_d_wu
);
359 DEFINE_XFTYPE(fcvt_d_wu
);
360 DEFINE_XFTYPE(fmv_d_x
);
361 DEFINE_FXTYPE(fcvt_l_d
);
362 DEFINE_FXTYPE(fcvt_lu_d
);
363 DEFINE_FXTYPE(fcvt_w_d
);
364 DEFINE_FXTYPE(fcvt_wu_d
);
365 DEFINE_FXTYPE(fmv_x_d
);
366 DEFINE_FXTYPE(feq_d
);
367 DEFINE_FXTYPE(flt_d
);
368 DEFINE_FXTYPE(fle_d
);
370 // provide a default disassembly for all instructions as a fallback
371 #define DECLARE_INSN(code, match, mask) \
372 add_insn(new disasm_insn_t(#code " (args unknown)", match, mask, {}));
373 #include "encoding.h"
377 const disasm_insn_t
* disassembler_t::lookup(insn_t insn
)
379 size_t idx
= insn
.bits() % HASH_SIZE
;
380 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
381 if(*chain
[idx
][j
] == insn
)
382 return chain
[idx
][j
];
385 for (size_t j
= 0; j
< chain
[idx
].size(); j
++)
386 if(*chain
[idx
][j
] == insn
)
387 return chain
[idx
][j
];
392 void disassembler_t::add_insn(disasm_insn_t
* insn
)
394 size_t idx
= HASH_SIZE
;
395 if (insn
->get_mask() % HASH_SIZE
== HASH_SIZE
- 1)
396 idx
= insn
->get_match() % HASH_SIZE
;
397 chain
[idx
].push_back(insn
);
400 disassembler_t::~disassembler_t()
402 for (size_t i
= 0; i
< HASH_SIZE
+1; i
++)
403 for (size_t j
= 0; j
< chain
[i
].size(); j
++)