1 // See LICENSE for license details.
3 #ifndef RISCV_CSR_ENCODING_H
4 #define RISCV_CSR_ENCODING_H
6 #define MSTATUS_UIE 0x00000001
7 #define MSTATUS_SIE 0x00000002
8 #define MSTATUS_HIE 0x00000004
9 #define MSTATUS_MIE 0x00000008
10 #define MSTATUS_UPIE 0x00000010
11 #define MSTATUS_SPIE 0x00000020
12 #define MSTATUS_HPIE 0x00000040
13 #define MSTATUS_MPIE 0x00000080
14 #define MSTATUS_SPP 0x00000100
15 #define MSTATUS_HPP 0x00000600
16 #define MSTATUS_MPP 0x00001800
17 #define MSTATUS_FS 0x00006000
18 #define MSTATUS_XS 0x00018000
19 #define MSTATUS_MPRV 0x00020000
20 #define MSTATUS_PUM 0x00040000
21 #define MSTATUS_MXR 0x00080000
22 #define MSTATUS_VM 0x1F000000
23 #define MSTATUS32_SD 0x80000000
24 #define MSTATUS64_SD 0x8000000000000000
26 #define SSTATUS_UIE 0x00000001
27 #define SSTATUS_SIE 0x00000002
28 #define SSTATUS_UPIE 0x00000010
29 #define SSTATUS_SPIE 0x00000020
30 #define SSTATUS_SPP 0x00000100
31 #define SSTATUS_FS 0x00006000
32 #define SSTATUS_XS 0x00018000
33 #define SSTATUS_PUM 0x00040000
34 #define SSTATUS32_SD 0x80000000
35 #define SSTATUS64_SD 0x8000000000000000
37 #define DCSR_XDEBUGVER (3U<<30)
38 #define DCSR_NDRESET (1<<29)
39 #define DCSR_FULLRESET (1<<28)
40 #define DCSR_HWBPCOUNT (0xfff<<16)
41 #define DCSR_EBREAKM (1<<15)
42 #define DCSR_EBREAKH (1<<14)
43 #define DCSR_EBREAKS (1<<13)
44 #define DCSR_EBREAKU (1<<12)
45 #define DCSR_STOPCYCLE (1<<10)
46 #define DCSR_STOPTIME (1<<9)
47 #define DCSR_CAUSE (7<<6)
48 #define DCSR_DEBUGINT (1<<5)
49 #define DCSR_HALT (1<<3)
50 #define DCSR_STEP (1<<2)
51 #define DCSR_PRV (3<<0)
53 #define DCSR_CAUSE_NONE 0
54 #define DCSR_CAUSE_SWBP 1
55 #define DCSR_CAUSE_HWBP 2
56 #define DCSR_CAUSE_DEBUGINT 3
57 #define DCSR_CAUSE_STEP 4
58 #define DCSR_CAUSE_HALT 5
60 #define MCONTROL_SELECT (1<<19)
61 #define MCONTROL_ACTION (0x7f<<12)
62 #define MCONTROL_CHAIN (1<<11)
63 #define MCONTROL_MATCH (0xf<<7)
64 #define MCONTROL_M (1<<6)
65 #define MCONTROL_H (1<<5)
66 #define MCONTROL_S (1<<4)
67 #define MCONTROL_U (1<<3)
68 #define MCONTROL_EXECUTE (1<<2)
69 #define MCONTROL_STORE (1<<1)
70 #define MCONTROL_LOAD (1<<0)
72 #define MCONTROL_ACTION_NONE 0
73 #define MCONTROL_ACTION_DEBUG_EXCEPTION 1
74 #define MCONTROL_ACTION_DEBUG_MODE 2
75 #define MCONTROL_ACTION_TRACE_START 3
76 #define MCONTROL_ACTION_TRACE_STOP 4
77 #define MCONTROL_ACTION_TRACE_EMIT 5
79 #define MCONTROL_MATCH_EQUAL 0
80 #define MCONTROL_MATCH_NAPOT 1
81 #define MCONTROL_MATCH_GE 2
82 #define MCONTROL_MATCH_LT 3
83 #define MCONTROL_MATCH_MASK_LOW 4
84 #define MCONTROL_MATCH_MASK_HIGH 5
86 #define MIP_SSIP (1 << IRQ_S_SOFT)
87 #define MIP_HSIP (1 << IRQ_H_SOFT)
88 #define MIP_MSIP (1 << IRQ_M_SOFT)
89 #define MIP_STIP (1 << IRQ_S_TIMER)
90 #define MIP_HTIP (1 << IRQ_H_TIMER)
91 #define MIP_MTIP (1 << IRQ_M_TIMER)
92 #define MIP_SEIP (1 << IRQ_S_EXT)
93 #define MIP_HEIP (1 << IRQ_H_EXT)
94 #define MIP_MEIP (1 << IRQ_M_EXT)
96 #define SIP_SSIP MIP_SSIP
97 #define SIP_STIP MIP_STIP
114 #define IRQ_S_TIMER 5
115 #define IRQ_H_TIMER 6
116 #define IRQ_M_TIMER 7
123 #define DEFAULT_RSTVEC 0x00001000
124 #define DEFAULT_NMIVEC 0x00001004
125 #define DEFAULT_MTVEC 0x00001010
126 #define CONFIG_STRING_ADDR 0x0000100C
127 #define EXT_IO_BASE 0x40000000
128 #define DRAM_BASE 0x80000000
130 // breakpoint control fields
131 #define BPCONTROL_X 0x00000001
132 #define BPCONTROL_W 0x00000002
133 #define BPCONTROL_R 0x00000004
134 #define BPCONTROL_U 0x00000008
135 #define BPCONTROL_S 0x00000010
136 #define BPCONTROL_H 0x00000020
137 #define BPCONTROL_M 0x00000040
138 #define BPCONTROL_BPMATCH 0x00000780
140 # define BPCONTROL_BPAMASKMAX 0x0F80000000000000
141 # define BPCONTROL_TDRTYPE 0xF000000000000000
143 # define BPCONTROL_BPAMASKMAX 0x0F800000
144 # define BPCONTROL_TDRTYPE 0xF0000000
147 // page table entry (PTE) fields
148 #define PTE_V 0x001 // Valid
149 #define PTE_R 0x002 // Read
150 #define PTE_W 0x004 // Write
151 #define PTE_X 0x008 // Execute
152 #define PTE_U 0x010 // User
153 #define PTE_G 0x020 // Global
154 #define PTE_A 0x040 // Accessed
155 #define PTE_D 0x080 // Dirty
156 #define PTE_SOFT 0x300 // Reserved for Software
158 #define PTE_PPN_SHIFT 10
160 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
165 # define MSTATUS_SD MSTATUS64_SD
166 # define SSTATUS_SD SSTATUS64_SD
167 # define RISCV_PGLEVEL_BITS 9
169 # define MSTATUS_SD MSTATUS32_SD
170 # define SSTATUS_SD SSTATUS32_SD
171 # define RISCV_PGLEVEL_BITS 10
173 #define RISCV_PGSHIFT 12
174 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
176 #ifndef __ASSEMBLER__
180 #define read_csr(reg) ({ unsigned long __tmp; \
181 asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
184 #define write_csr(reg, val) ({ \
185 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
186 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
188 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
190 #define swap_csr(reg, val) ({ unsigned long __tmp; \
191 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
192 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
194 asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
197 #define set_csr(reg, bit) ({ unsigned long __tmp; \
198 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
199 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
201 asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
204 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
205 if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
206 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
208 asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
211 #define rdtime() read_csr(time)
212 #define rdcycle() read_csr(cycle)
213 #define rdinstret() read_csr(instret)
222 /* Automatically generated by parse-opcodes */
223 #ifndef RISCV_ENCODING_H
224 #define RISCV_ENCODING_H
225 #define MATCH_BEQ 0x63
226 #define MASK_BEQ 0x707f
227 #define MATCH_BNE 0x1063
228 #define MASK_BNE 0x707f
229 #define MATCH_BLT 0x4063
230 #define MASK_BLT 0x707f
231 #define MATCH_BGE 0x5063
232 #define MASK_BGE 0x707f
233 #define MATCH_BLTU 0x6063
234 #define MASK_BLTU 0x707f
235 #define MATCH_BGEU 0x7063
236 #define MASK_BGEU 0x707f
237 #define MATCH_JALR 0x67
238 #define MASK_JALR 0x707f
239 #define MATCH_JAL 0x6f
240 #define MASK_JAL 0x7f
241 #define MATCH_LUI 0x37
242 #define MASK_LUI 0x7f
243 #define MATCH_AUIPC 0x17
244 #define MASK_AUIPC 0x7f
245 #define MATCH_ADDI 0x13
246 #define MASK_ADDI 0x707f
247 #define MATCH_SLLI 0x1013
248 #define MASK_SLLI 0xfc00707f
249 #define MATCH_SLTI 0x2013
250 #define MASK_SLTI 0x707f
251 #define MATCH_SLTIU 0x3013
252 #define MASK_SLTIU 0x707f
253 #define MATCH_XORI 0x4013
254 #define MASK_XORI 0x707f
255 #define MATCH_SRLI 0x5013
256 #define MASK_SRLI 0xfc00707f
257 #define MATCH_SRAI 0x40005013
258 #define MASK_SRAI 0xfc00707f
259 #define MATCH_ORI 0x6013
260 #define MASK_ORI 0x707f
261 #define MATCH_ANDI 0x7013
262 #define MASK_ANDI 0x707f
263 #define MATCH_ADD 0x33
264 #define MASK_ADD 0xfe00707f
265 #define MATCH_SUB 0x40000033
266 #define MASK_SUB 0xfe00707f
267 #define MATCH_SLL 0x1033
268 #define MASK_SLL 0xfe00707f
269 #define MATCH_SLT 0x2033
270 #define MASK_SLT 0xfe00707f
271 #define MATCH_SLTU 0x3033
272 #define MASK_SLTU 0xfe00707f
273 #define MATCH_XOR 0x4033
274 #define MASK_XOR 0xfe00707f
275 #define MATCH_SRL 0x5033
276 #define MASK_SRL 0xfe00707f
277 #define MATCH_SRA 0x40005033
278 #define MASK_SRA 0xfe00707f
279 #define MATCH_OR 0x6033
280 #define MASK_OR 0xfe00707f
281 #define MATCH_AND 0x7033
282 #define MASK_AND 0xfe00707f
283 #define MATCH_ADDIW 0x1b
284 #define MASK_ADDIW 0x707f
285 #define MATCH_SLLIW 0x101b
286 #define MASK_SLLIW 0xfe00707f
287 #define MATCH_SRLIW 0x501b
288 #define MASK_SRLIW 0xfe00707f
289 #define MATCH_SRAIW 0x4000501b
290 #define MASK_SRAIW 0xfe00707f
291 #define MATCH_ADDW 0x3b
292 #define MASK_ADDW 0xfe00707f
293 #define MATCH_SUBW 0x4000003b
294 #define MASK_SUBW 0xfe00707f
295 #define MATCH_SLLW 0x103b
296 #define MASK_SLLW 0xfe00707f
297 #define MATCH_SRLW 0x503b
298 #define MASK_SRLW 0xfe00707f
299 #define MATCH_SRAW 0x4000503b
300 #define MASK_SRAW 0xfe00707f
302 #define MASK_LB 0x707f
303 #define MATCH_LH 0x1003
304 #define MASK_LH 0x707f
305 #define MATCH_LW 0x2003
306 #define MASK_LW 0x707f
307 #define MATCH_LD 0x3003
308 #define MASK_LD 0x707f
309 #define MATCH_LBU 0x4003
310 #define MASK_LBU 0x707f
311 #define MATCH_LHU 0x5003
312 #define MASK_LHU 0x707f
313 #define MATCH_LWU 0x6003
314 #define MASK_LWU 0x707f
315 #define MATCH_SB 0x23
316 #define MASK_SB 0x707f
317 #define MATCH_SH 0x1023
318 #define MASK_SH 0x707f
319 #define MATCH_SW 0x2023
320 #define MASK_SW 0x707f
321 #define MATCH_SD 0x3023
322 #define MASK_SD 0x707f
323 #define MATCH_FENCE 0xf
324 #define MASK_FENCE 0x707f
325 #define MATCH_FENCE_I 0x100f
326 #define MASK_FENCE_I 0x707f
327 #define MATCH_MUL 0x2000033
328 #define MASK_MUL 0xfe00707f
329 #define MATCH_MULH 0x2001033
330 #define MASK_MULH 0xfe00707f
331 #define MATCH_MULHSU 0x2002033
332 #define MASK_MULHSU 0xfe00707f
333 #define MATCH_MULHU 0x2003033
334 #define MASK_MULHU 0xfe00707f
335 #define MATCH_DIV 0x2004033
336 #define MASK_DIV 0xfe00707f
337 #define MATCH_DIVU 0x2005033
338 #define MASK_DIVU 0xfe00707f
339 #define MATCH_REM 0x2006033
340 #define MASK_REM 0xfe00707f
341 #define MATCH_REMU 0x2007033
342 #define MASK_REMU 0xfe00707f
343 #define MATCH_MULW 0x200003b
344 #define MASK_MULW 0xfe00707f
345 #define MATCH_DIVW 0x200403b
346 #define MASK_DIVW 0xfe00707f
347 #define MATCH_DIVUW 0x200503b
348 #define MASK_DIVUW 0xfe00707f
349 #define MATCH_REMW 0x200603b
350 #define MASK_REMW 0xfe00707f
351 #define MATCH_REMUW 0x200703b
352 #define MASK_REMUW 0xfe00707f
353 #define MATCH_AMOADD_W 0x202f
354 #define MASK_AMOADD_W 0xf800707f
355 #define MATCH_AMOXOR_W 0x2000202f
356 #define MASK_AMOXOR_W 0xf800707f
357 #define MATCH_AMOOR_W 0x4000202f
358 #define MASK_AMOOR_W 0xf800707f
359 #define MATCH_AMOAND_W 0x6000202f
360 #define MASK_AMOAND_W 0xf800707f
361 #define MATCH_AMOMIN_W 0x8000202f
362 #define MASK_AMOMIN_W 0xf800707f
363 #define MATCH_AMOMAX_W 0xa000202f
364 #define MASK_AMOMAX_W 0xf800707f
365 #define MATCH_AMOMINU_W 0xc000202f
366 #define MASK_AMOMINU_W 0xf800707f
367 #define MATCH_AMOMAXU_W 0xe000202f
368 #define MASK_AMOMAXU_W 0xf800707f
369 #define MATCH_AMOSWAP_W 0x800202f
370 #define MASK_AMOSWAP_W 0xf800707f
371 #define MATCH_LR_W 0x1000202f
372 #define MASK_LR_W 0xf9f0707f
373 #define MATCH_SC_W 0x1800202f
374 #define MASK_SC_W 0xf800707f
375 #define MATCH_AMOADD_D 0x302f
376 #define MASK_AMOADD_D 0xf800707f
377 #define MATCH_AMOXOR_D 0x2000302f
378 #define MASK_AMOXOR_D 0xf800707f
379 #define MATCH_AMOOR_D 0x4000302f
380 #define MASK_AMOOR_D 0xf800707f
381 #define MATCH_AMOAND_D 0x6000302f
382 #define MASK_AMOAND_D 0xf800707f
383 #define MATCH_AMOMIN_D 0x8000302f
384 #define MASK_AMOMIN_D 0xf800707f
385 #define MATCH_AMOMAX_D 0xa000302f
386 #define MASK_AMOMAX_D 0xf800707f
387 #define MATCH_AMOMINU_D 0xc000302f
388 #define MASK_AMOMINU_D 0xf800707f
389 #define MATCH_AMOMAXU_D 0xe000302f
390 #define MASK_AMOMAXU_D 0xf800707f
391 #define MATCH_AMOSWAP_D 0x800302f
392 #define MASK_AMOSWAP_D 0xf800707f
393 #define MATCH_LR_D 0x1000302f
394 #define MASK_LR_D 0xf9f0707f
395 #define MATCH_SC_D 0x1800302f
396 #define MASK_SC_D 0xf800707f
397 #define MATCH_ECALL 0x73
398 #define MASK_ECALL 0xffffffff
399 #define MATCH_EBREAK 0x100073
400 #define MASK_EBREAK 0xffffffff
401 #define MATCH_URET 0x200073
402 #define MASK_URET 0xffffffff
403 #define MATCH_SRET 0x10200073
404 #define MASK_SRET 0xffffffff
405 #define MATCH_HRET 0x20200073
406 #define MASK_HRET 0xffffffff
407 #define MATCH_MRET 0x30200073
408 #define MASK_MRET 0xffffffff
409 #define MATCH_DRET 0x7b200073
410 #define MASK_DRET 0xffffffff
411 #define MATCH_SFENCE_VM 0x10400073
412 #define MASK_SFENCE_VM 0xfff07fff
413 #define MATCH_WFI 0x10500073
414 #define MASK_WFI 0xffffffff
415 #define MATCH_CSRRW 0x1073
416 #define MASK_CSRRW 0x707f
417 #define MATCH_CSRRS 0x2073
418 #define MASK_CSRRS 0x707f
419 #define MATCH_CSRRC 0x3073
420 #define MASK_CSRRC 0x707f
421 #define MATCH_CSRRWI 0x5073
422 #define MASK_CSRRWI 0x707f
423 #define MATCH_CSRRSI 0x6073
424 #define MASK_CSRRSI 0x707f
425 #define MATCH_CSRRCI 0x7073
426 #define MASK_CSRRCI 0x707f
427 #define MATCH_FADD_S 0x53
428 #define MASK_FADD_S 0xfe00007f
429 #define MATCH_FSUB_S 0x8000053
430 #define MASK_FSUB_S 0xfe00007f
431 #define MATCH_FMUL_S 0x10000053
432 #define MASK_FMUL_S 0xfe00007f
433 #define MATCH_FDIV_S 0x18000053
434 #define MASK_FDIV_S 0xfe00007f
435 #define MATCH_FSGNJ_S 0x20000053
436 #define MASK_FSGNJ_S 0xfe00707f
437 #define MATCH_FSGNJN_S 0x20001053
438 #define MASK_FSGNJN_S 0xfe00707f
439 #define MATCH_FSGNJX_S 0x20002053
440 #define MASK_FSGNJX_S 0xfe00707f
441 #define MATCH_FMIN_S 0x28000053
442 #define MASK_FMIN_S 0xfe00707f
443 #define MATCH_FMAX_S 0x28001053
444 #define MASK_FMAX_S 0xfe00707f
445 #define MATCH_FSQRT_S 0x58000053
446 #define MASK_FSQRT_S 0xfff0007f
447 #define MATCH_FADD_D 0x2000053
448 #define MASK_FADD_D 0xfe00007f
449 #define MATCH_FSUB_D 0xa000053
450 #define MASK_FSUB_D 0xfe00007f
451 #define MATCH_FMUL_D 0x12000053
452 #define MASK_FMUL_D 0xfe00007f
453 #define MATCH_FDIV_D 0x1a000053
454 #define MASK_FDIV_D 0xfe00007f
455 #define MATCH_FSGNJ_D 0x22000053
456 #define MASK_FSGNJ_D 0xfe00707f
457 #define MATCH_FSGNJN_D 0x22001053
458 #define MASK_FSGNJN_D 0xfe00707f
459 #define MATCH_FSGNJX_D 0x22002053
460 #define MASK_FSGNJX_D 0xfe00707f
461 #define MATCH_FMIN_D 0x2a000053
462 #define MASK_FMIN_D 0xfe00707f
463 #define MATCH_FMAX_D 0x2a001053
464 #define MASK_FMAX_D 0xfe00707f
465 #define MATCH_FCVT_S_D 0x40100053
466 #define MASK_FCVT_S_D 0xfff0007f
467 #define MATCH_FCVT_D_S 0x42000053
468 #define MASK_FCVT_D_S 0xfff0007f
469 #define MATCH_FSQRT_D 0x5a000053
470 #define MASK_FSQRT_D 0xfff0007f
471 #define MATCH_FLE_S 0xa0000053
472 #define MASK_FLE_S 0xfe00707f
473 #define MATCH_FLT_S 0xa0001053
474 #define MASK_FLT_S 0xfe00707f
475 #define MATCH_FEQ_S 0xa0002053
476 #define MASK_FEQ_S 0xfe00707f
477 #define MATCH_FLE_D 0xa2000053
478 #define MASK_FLE_D 0xfe00707f
479 #define MATCH_FLT_D 0xa2001053
480 #define MASK_FLT_D 0xfe00707f
481 #define MATCH_FEQ_D 0xa2002053
482 #define MASK_FEQ_D 0xfe00707f
483 #define MATCH_FCVT_W_S 0xc0000053
484 #define MASK_FCVT_W_S 0xfff0007f
485 #define MATCH_FCVT_WU_S 0xc0100053
486 #define MASK_FCVT_WU_S 0xfff0007f
487 #define MATCH_FCVT_L_S 0xc0200053
488 #define MASK_FCVT_L_S 0xfff0007f
489 #define MATCH_FCVT_LU_S 0xc0300053
490 #define MASK_FCVT_LU_S 0xfff0007f
491 #define MATCH_FMV_X_S 0xe0000053
492 #define MASK_FMV_X_S 0xfff0707f
493 #define MATCH_FCLASS_S 0xe0001053
494 #define MASK_FCLASS_S 0xfff0707f
495 #define MATCH_FCVT_W_D 0xc2000053
496 #define MASK_FCVT_W_D 0xfff0007f
497 #define MATCH_FCVT_WU_D 0xc2100053
498 #define MASK_FCVT_WU_D 0xfff0007f
499 #define MATCH_FCVT_L_D 0xc2200053
500 #define MASK_FCVT_L_D 0xfff0007f
501 #define MATCH_FCVT_LU_D 0xc2300053
502 #define MASK_FCVT_LU_D 0xfff0007f
503 #define MATCH_FMV_X_D 0xe2000053
504 #define MASK_FMV_X_D 0xfff0707f
505 #define MATCH_FCLASS_D 0xe2001053
506 #define MASK_FCLASS_D 0xfff0707f
507 #define MATCH_FCVT_S_W 0xd0000053
508 #define MASK_FCVT_S_W 0xfff0007f
509 #define MATCH_FCVT_S_WU 0xd0100053
510 #define MASK_FCVT_S_WU 0xfff0007f
511 #define MATCH_FCVT_S_L 0xd0200053
512 #define MASK_FCVT_S_L 0xfff0007f
513 #define MATCH_FCVT_S_LU 0xd0300053
514 #define MASK_FCVT_S_LU 0xfff0007f
515 #define MATCH_FMV_S_X 0xf0000053
516 #define MASK_FMV_S_X 0xfff0707f
517 #define MATCH_FCVT_D_W 0xd2000053
518 #define MASK_FCVT_D_W 0xfff0007f
519 #define MATCH_FCVT_D_WU 0xd2100053
520 #define MASK_FCVT_D_WU 0xfff0007f
521 #define MATCH_FCVT_D_L 0xd2200053
522 #define MASK_FCVT_D_L 0xfff0007f
523 #define MATCH_FCVT_D_LU 0xd2300053
524 #define MASK_FCVT_D_LU 0xfff0007f
525 #define MATCH_FMV_D_X 0xf2000053
526 #define MASK_FMV_D_X 0xfff0707f
527 #define MATCH_FLW 0x2007
528 #define MASK_FLW 0x707f
529 #define MATCH_FLD 0x3007
530 #define MASK_FLD 0x707f
531 #define MATCH_FSW 0x2027
532 #define MASK_FSW 0x707f
533 #define MATCH_FSD 0x3027
534 #define MASK_FSD 0x707f
535 #define MATCH_FMADD_S 0x43
536 #define MASK_FMADD_S 0x600007f
537 #define MATCH_FMSUB_S 0x47
538 #define MASK_FMSUB_S 0x600007f
539 #define MATCH_FNMSUB_S 0x4b
540 #define MASK_FNMSUB_S 0x600007f
541 #define MATCH_FNMADD_S 0x4f
542 #define MASK_FNMADD_S 0x600007f
543 #define MATCH_FMADD_D 0x2000043
544 #define MASK_FMADD_D 0x600007f
545 #define MATCH_FMSUB_D 0x2000047
546 #define MASK_FMSUB_D 0x600007f
547 #define MATCH_FNMSUB_D 0x200004b
548 #define MASK_FNMSUB_D 0x600007f
549 #define MATCH_FNMADD_D 0x200004f
550 #define MASK_FNMADD_D 0x600007f
551 #define MATCH_C_NOP 0x1
552 #define MASK_C_NOP 0xffff
553 #define MATCH_C_ADDI16SP 0x6101
554 #define MASK_C_ADDI16SP 0xef83
555 #define MATCH_C_JR 0x8002
556 #define MASK_C_JR 0xf07f
557 #define MATCH_C_JALR 0x9002
558 #define MASK_C_JALR 0xf07f
559 #define MATCH_C_EBREAK 0x9002
560 #define MASK_C_EBREAK 0xffff
561 #define MATCH_C_LD 0x6000
562 #define MASK_C_LD 0xe003
563 #define MATCH_C_SD 0xe000
564 #define MASK_C_SD 0xe003
565 #define MATCH_C_ADDIW 0x2001
566 #define MASK_C_ADDIW 0xe003
567 #define MATCH_C_LDSP 0x6002
568 #define MASK_C_LDSP 0xe003
569 #define MATCH_C_SDSP 0xe002
570 #define MASK_C_SDSP 0xe003
571 #define MATCH_C_ADDI4SPN 0x0
572 #define MASK_C_ADDI4SPN 0xe003
573 #define MATCH_C_FLD 0x2000
574 #define MASK_C_FLD 0xe003
575 #define MATCH_C_LW 0x4000
576 #define MASK_C_LW 0xe003
577 #define MATCH_C_FLW 0x6000
578 #define MASK_C_FLW 0xe003
579 #define MATCH_C_FSD 0xa000
580 #define MASK_C_FSD 0xe003
581 #define MATCH_C_SW 0xc000
582 #define MASK_C_SW 0xe003
583 #define MATCH_C_FSW 0xe000
584 #define MASK_C_FSW 0xe003
585 #define MATCH_C_ADDI 0x1
586 #define MASK_C_ADDI 0xe003
587 #define MATCH_C_JAL 0x2001
588 #define MASK_C_JAL 0xe003
589 #define MATCH_C_LI 0x4001
590 #define MASK_C_LI 0xe003
591 #define MATCH_C_LUI 0x6001
592 #define MASK_C_LUI 0xe003
593 #define MATCH_C_SRLI 0x8001
594 #define MASK_C_SRLI 0xec03
595 #define MATCH_C_SRAI 0x8401
596 #define MASK_C_SRAI 0xec03
597 #define MATCH_C_ANDI 0x8801
598 #define MASK_C_ANDI 0xec03
599 #define MATCH_C_SUB 0x8c01
600 #define MASK_C_SUB 0xfc63
601 #define MATCH_C_XOR 0x8c21
602 #define MASK_C_XOR 0xfc63
603 #define MATCH_C_OR 0x8c41
604 #define MASK_C_OR 0xfc63
605 #define MATCH_C_AND 0x8c61
606 #define MASK_C_AND 0xfc63
607 #define MATCH_C_SUBW 0x9c01
608 #define MASK_C_SUBW 0xfc63
609 #define MATCH_C_ADDW 0x9c21
610 #define MASK_C_ADDW 0xfc63
611 #define MATCH_C_J 0xa001
612 #define MASK_C_J 0xe003
613 #define MATCH_C_BEQZ 0xc001
614 #define MASK_C_BEQZ 0xe003
615 #define MATCH_C_BNEZ 0xe001
616 #define MASK_C_BNEZ 0xe003
617 #define MATCH_C_SLLI 0x2
618 #define MASK_C_SLLI 0xe003
619 #define MATCH_C_FLDSP 0x2002
620 #define MASK_C_FLDSP 0xe003
621 #define MATCH_C_LWSP 0x4002
622 #define MASK_C_LWSP 0xe003
623 #define MATCH_C_FLWSP 0x6002
624 #define MASK_C_FLWSP 0xe003
625 #define MATCH_C_MV 0x8002
626 #define MASK_C_MV 0xf003
627 #define MATCH_C_ADD 0x9002
628 #define MASK_C_ADD 0xf003
629 #define MATCH_C_FSDSP 0xa002
630 #define MASK_C_FSDSP 0xe003
631 #define MATCH_C_SWSP 0xc002
632 #define MASK_C_SWSP 0xe003
633 #define MATCH_C_FSWSP 0xe002
634 #define MASK_C_FSWSP 0xe003
635 #define MATCH_CUSTOM0 0xb
636 #define MASK_CUSTOM0 0x707f
637 #define MATCH_CUSTOM0_RS1 0x200b
638 #define MASK_CUSTOM0_RS1 0x707f
639 #define MATCH_CUSTOM0_RS1_RS2 0x300b
640 #define MASK_CUSTOM0_RS1_RS2 0x707f
641 #define MATCH_CUSTOM0_RD 0x400b
642 #define MASK_CUSTOM0_RD 0x707f
643 #define MATCH_CUSTOM0_RD_RS1 0x600b
644 #define MASK_CUSTOM0_RD_RS1 0x707f
645 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
646 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f
647 #define MATCH_CUSTOM1 0x2b
648 #define MASK_CUSTOM1 0x707f
649 #define MATCH_CUSTOM1_RS1 0x202b
650 #define MASK_CUSTOM1_RS1 0x707f
651 #define MATCH_CUSTOM1_RS1_RS2 0x302b
652 #define MASK_CUSTOM1_RS1_RS2 0x707f
653 #define MATCH_CUSTOM1_RD 0x402b
654 #define MASK_CUSTOM1_RD 0x707f
655 #define MATCH_CUSTOM1_RD_RS1 0x602b
656 #define MASK_CUSTOM1_RD_RS1 0x707f
657 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
658 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f
659 #define MATCH_CUSTOM2 0x5b
660 #define MASK_CUSTOM2 0x707f
661 #define MATCH_CUSTOM2_RS1 0x205b
662 #define MASK_CUSTOM2_RS1 0x707f
663 #define MATCH_CUSTOM2_RS1_RS2 0x305b
664 #define MASK_CUSTOM2_RS1_RS2 0x707f
665 #define MATCH_CUSTOM2_RD 0x405b
666 #define MASK_CUSTOM2_RD 0x707f
667 #define MATCH_CUSTOM2_RD_RS1 0x605b
668 #define MASK_CUSTOM2_RD_RS1 0x707f
669 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
670 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f
671 #define MATCH_CUSTOM3 0x7b
672 #define MASK_CUSTOM3 0x707f
673 #define MATCH_CUSTOM3_RS1 0x207b
674 #define MASK_CUSTOM3_RS1 0x707f
675 #define MATCH_CUSTOM3_RS1_RS2 0x307b
676 #define MASK_CUSTOM3_RS1_RS2 0x707f
677 #define MATCH_CUSTOM3_RD 0x407b
678 #define MASK_CUSTOM3_RD 0x707f
679 #define MATCH_CUSTOM3_RD_RS1 0x607b
680 #define MASK_CUSTOM3_RD_RS1 0x707f
681 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
682 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
683 #define CSR_FFLAGS 0x1
686 #define CSR_CYCLE 0xc00
687 #define CSR_TIME 0xc01
688 #define CSR_INSTRET 0xc02
689 #define CSR_SSTATUS 0x100
690 #define CSR_SIE 0x104
691 #define CSR_STVEC 0x105
692 #define CSR_SSCRATCH 0x140
693 #define CSR_SEPC 0x141
694 #define CSR_SCAUSE 0x142
695 #define CSR_SBADADDR 0x143
696 #define CSR_SIP 0x144
697 #define CSR_SPTBR 0x180
698 #define CSR_SCYCLE 0xd00
699 #define CSR_STIME 0xd01
700 #define CSR_SINSTRET 0xd02
701 #define CSR_MSTATUS 0x300
702 #define CSR_MEDELEG 0x302
703 #define CSR_MIDELEG 0x303
704 #define CSR_MIE 0x304
705 #define CSR_MTVEC 0x305
706 #define CSR_MSCRATCH 0x340
707 #define CSR_MEPC 0x341
708 #define CSR_MCAUSE 0x342
709 #define CSR_MBADADDR 0x343
710 #define CSR_MIP 0x344
711 #define CSR_MUCOUNTEREN 0x310
712 #define CSR_MSCOUNTEREN 0x311
713 #define CSR_MUCYCLE_DELTA 0x700
714 #define CSR_MUTIME_DELTA 0x701
715 #define CSR_MUINSTRET_DELTA 0x702
716 #define CSR_MSCYCLE_DELTA 0x704
717 #define CSR_MSTIME_DELTA 0x705
718 #define CSR_MSINSTRET_DELTA 0x706
719 #define CSR_TSELECT 0x7a0
720 #define CSR_TDATA0 0x7a1
721 #define CSR_TDATA1 0x7a2
722 #define CSR_TDATA2 0x7a3
723 #define CSR_DCSR 0x7b0
724 #define CSR_DPC 0x7b1
725 #define CSR_DSCRATCH 0x7b2
726 #define CSR_MCYCLE 0xf00
727 #define CSR_MTIME 0xf01
728 #define CSR_MINSTRET 0xf02
729 #define CSR_MISA 0xf10
730 #define CSR_MVENDORID 0xf11
731 #define CSR_MARCHID 0xf12
732 #define CSR_MIMPID 0xf13
733 #define CSR_MHARTID 0xf14
734 #define CSR_MRESET 0x7c2
735 #define CSR_CYCLEH 0xc80
736 #define CSR_TIMEH 0xc81
737 #define CSR_INSTRETH 0xc82
738 #define CSR_MUCYCLE_DELTAH 0x780
739 #define CSR_MUTIME_DELTAH 0x781
740 #define CSR_MUINSTRET_DELTAH 0x782
741 #define CSR_MSCYCLE_DELTAH 0x784
742 #define CSR_MSTIME_DELTAH 0x785
743 #define CSR_MSINSTRET_DELTAH 0x786
744 #define CSR_MCYCLEH 0xf80
745 #define CSR_MTIMEH 0xf81
746 #define CSR_MINSTRETH 0xf82
747 #define CAUSE_MISALIGNED_FETCH 0x0
748 #define CAUSE_FAULT_FETCH 0x1
749 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
750 #define CAUSE_BREAKPOINT 0x3
751 #define CAUSE_MISALIGNED_LOAD 0x4
752 #define CAUSE_FAULT_LOAD 0x5
753 #define CAUSE_MISALIGNED_STORE 0x6
754 #define CAUSE_FAULT_STORE 0x7
755 #define CAUSE_USER_ECALL 0x8
756 #define CAUSE_SUPERVISOR_ECALL 0x9
757 #define CAUSE_HYPERVISOR_ECALL 0xa
758 #define CAUSE_MACHINE_ECALL 0xb
761 DECLARE_INSN(beq
, MATCH_BEQ
, MASK_BEQ
)
762 DECLARE_INSN(bne
, MATCH_BNE
, MASK_BNE
)
763 DECLARE_INSN(blt
, MATCH_BLT
, MASK_BLT
)
764 DECLARE_INSN(bge
, MATCH_BGE
, MASK_BGE
)
765 DECLARE_INSN(bltu
, MATCH_BLTU
, MASK_BLTU
)
766 DECLARE_INSN(bgeu
, MATCH_BGEU
, MASK_BGEU
)
767 DECLARE_INSN(jalr
, MATCH_JALR
, MASK_JALR
)
768 DECLARE_INSN(jal
, MATCH_JAL
, MASK_JAL
)
769 DECLARE_INSN(lui
, MATCH_LUI
, MASK_LUI
)
770 DECLARE_INSN(auipc
, MATCH_AUIPC
, MASK_AUIPC
)
771 DECLARE_INSN(addi
, MATCH_ADDI
, MASK_ADDI
)
772 DECLARE_INSN(slli
, MATCH_SLLI
, MASK_SLLI
)
773 DECLARE_INSN(slti
, MATCH_SLTI
, MASK_SLTI
)
774 DECLARE_INSN(sltiu
, MATCH_SLTIU
, MASK_SLTIU
)
775 DECLARE_INSN(xori
, MATCH_XORI
, MASK_XORI
)
776 DECLARE_INSN(srli
, MATCH_SRLI
, MASK_SRLI
)
777 DECLARE_INSN(srai
, MATCH_SRAI
, MASK_SRAI
)
778 DECLARE_INSN(ori
, MATCH_ORI
, MASK_ORI
)
779 DECLARE_INSN(andi
, MATCH_ANDI
, MASK_ANDI
)
780 DECLARE_INSN(add
, MATCH_ADD
, MASK_ADD
)
781 DECLARE_INSN(sub
, MATCH_SUB
, MASK_SUB
)
782 DECLARE_INSN(sll
, MATCH_SLL
, MASK_SLL
)
783 DECLARE_INSN(slt
, MATCH_SLT
, MASK_SLT
)
784 DECLARE_INSN(sltu
, MATCH_SLTU
, MASK_SLTU
)
785 DECLARE_INSN(xor, MATCH_XOR
, MASK_XOR
)
786 DECLARE_INSN(srl
, MATCH_SRL
, MASK_SRL
)
787 DECLARE_INSN(sra
, MATCH_SRA
, MASK_SRA
)
788 DECLARE_INSN(or, MATCH_OR
, MASK_OR
)
789 DECLARE_INSN(and, MATCH_AND
, MASK_AND
)
790 DECLARE_INSN(addiw
, MATCH_ADDIW
, MASK_ADDIW
)
791 DECLARE_INSN(slliw
, MATCH_SLLIW
, MASK_SLLIW
)
792 DECLARE_INSN(srliw
, MATCH_SRLIW
, MASK_SRLIW
)
793 DECLARE_INSN(sraiw
, MATCH_SRAIW
, MASK_SRAIW
)
794 DECLARE_INSN(addw
, MATCH_ADDW
, MASK_ADDW
)
795 DECLARE_INSN(subw
, MATCH_SUBW
, MASK_SUBW
)
796 DECLARE_INSN(sllw
, MATCH_SLLW
, MASK_SLLW
)
797 DECLARE_INSN(srlw
, MATCH_SRLW
, MASK_SRLW
)
798 DECLARE_INSN(sraw
, MATCH_SRAW
, MASK_SRAW
)
799 DECLARE_INSN(lb
, MATCH_LB
, MASK_LB
)
800 DECLARE_INSN(lh
, MATCH_LH
, MASK_LH
)
801 DECLARE_INSN(lw
, MATCH_LW
, MASK_LW
)
802 DECLARE_INSN(ld
, MATCH_LD
, MASK_LD
)
803 DECLARE_INSN(lbu
, MATCH_LBU
, MASK_LBU
)
804 DECLARE_INSN(lhu
, MATCH_LHU
, MASK_LHU
)
805 DECLARE_INSN(lwu
, MATCH_LWU
, MASK_LWU
)
806 DECLARE_INSN(sb
, MATCH_SB
, MASK_SB
)
807 DECLARE_INSN(sh
, MATCH_SH
, MASK_SH
)
808 DECLARE_INSN(sw
, MATCH_SW
, MASK_SW
)
809 DECLARE_INSN(sd
, MATCH_SD
, MASK_SD
)
810 DECLARE_INSN(fence
, MATCH_FENCE
, MASK_FENCE
)
811 DECLARE_INSN(fence_i
, MATCH_FENCE_I
, MASK_FENCE_I
)
812 DECLARE_INSN(mul
, MATCH_MUL
, MASK_MUL
)
813 DECLARE_INSN(mulh
, MATCH_MULH
, MASK_MULH
)
814 DECLARE_INSN(mulhsu
, MATCH_MULHSU
, MASK_MULHSU
)
815 DECLARE_INSN(mulhu
, MATCH_MULHU
, MASK_MULHU
)
816 DECLARE_INSN(div
, MATCH_DIV
, MASK_DIV
)
817 DECLARE_INSN(divu
, MATCH_DIVU
, MASK_DIVU
)
818 DECLARE_INSN(rem
, MATCH_REM
, MASK_REM
)
819 DECLARE_INSN(remu
, MATCH_REMU
, MASK_REMU
)
820 DECLARE_INSN(mulw
, MATCH_MULW
, MASK_MULW
)
821 DECLARE_INSN(divw
, MATCH_DIVW
, MASK_DIVW
)
822 DECLARE_INSN(divuw
, MATCH_DIVUW
, MASK_DIVUW
)
823 DECLARE_INSN(remw
, MATCH_REMW
, MASK_REMW
)
824 DECLARE_INSN(remuw
, MATCH_REMUW
, MASK_REMUW
)
825 DECLARE_INSN(amoadd_w
, MATCH_AMOADD_W
, MASK_AMOADD_W
)
826 DECLARE_INSN(amoxor_w
, MATCH_AMOXOR_W
, MASK_AMOXOR_W
)
827 DECLARE_INSN(amoor_w
, MATCH_AMOOR_W
, MASK_AMOOR_W
)
828 DECLARE_INSN(amoand_w
, MATCH_AMOAND_W
, MASK_AMOAND_W
)
829 DECLARE_INSN(amomin_w
, MATCH_AMOMIN_W
, MASK_AMOMIN_W
)
830 DECLARE_INSN(amomax_w
, MATCH_AMOMAX_W
, MASK_AMOMAX_W
)
831 DECLARE_INSN(amominu_w
, MATCH_AMOMINU_W
, MASK_AMOMINU_W
)
832 DECLARE_INSN(amomaxu_w
, MATCH_AMOMAXU_W
, MASK_AMOMAXU_W
)
833 DECLARE_INSN(amoswap_w
, MATCH_AMOSWAP_W
, MASK_AMOSWAP_W
)
834 DECLARE_INSN(lr_w
, MATCH_LR_W
, MASK_LR_W
)
835 DECLARE_INSN(sc_w
, MATCH_SC_W
, MASK_SC_W
)
836 DECLARE_INSN(amoadd_d
, MATCH_AMOADD_D
, MASK_AMOADD_D
)
837 DECLARE_INSN(amoxor_d
, MATCH_AMOXOR_D
, MASK_AMOXOR_D
)
838 DECLARE_INSN(amoor_d
, MATCH_AMOOR_D
, MASK_AMOOR_D
)
839 DECLARE_INSN(amoand_d
, MATCH_AMOAND_D
, MASK_AMOAND_D
)
840 DECLARE_INSN(amomin_d
, MATCH_AMOMIN_D
, MASK_AMOMIN_D
)
841 DECLARE_INSN(amomax_d
, MATCH_AMOMAX_D
, MASK_AMOMAX_D
)
842 DECLARE_INSN(amominu_d
, MATCH_AMOMINU_D
, MASK_AMOMINU_D
)
843 DECLARE_INSN(amomaxu_d
, MATCH_AMOMAXU_D
, MASK_AMOMAXU_D
)
844 DECLARE_INSN(amoswap_d
, MATCH_AMOSWAP_D
, MASK_AMOSWAP_D
)
845 DECLARE_INSN(lr_d
, MATCH_LR_D
, MASK_LR_D
)
846 DECLARE_INSN(sc_d
, MATCH_SC_D
, MASK_SC_D
)
847 DECLARE_INSN(ecall
, MATCH_ECALL
, MASK_ECALL
)
848 DECLARE_INSN(ebreak
, MATCH_EBREAK
, MASK_EBREAK
)
849 DECLARE_INSN(uret
, MATCH_URET
, MASK_URET
)
850 DECLARE_INSN(sret
, MATCH_SRET
, MASK_SRET
)
851 DECLARE_INSN(hret
, MATCH_HRET
, MASK_HRET
)
852 DECLARE_INSN(mret
, MATCH_MRET
, MASK_MRET
)
853 DECLARE_INSN(dret
, MATCH_DRET
, MASK_DRET
)
854 DECLARE_INSN(sfence_vm
, MATCH_SFENCE_VM
, MASK_SFENCE_VM
)
855 DECLARE_INSN(wfi
, MATCH_WFI
, MASK_WFI
)
856 DECLARE_INSN(csrrw
, MATCH_CSRRW
, MASK_CSRRW
)
857 DECLARE_INSN(csrrs
, MATCH_CSRRS
, MASK_CSRRS
)
858 DECLARE_INSN(csrrc
, MATCH_CSRRC
, MASK_CSRRC
)
859 DECLARE_INSN(csrrwi
, MATCH_CSRRWI
, MASK_CSRRWI
)
860 DECLARE_INSN(csrrsi
, MATCH_CSRRSI
, MASK_CSRRSI
)
861 DECLARE_INSN(csrrci
, MATCH_CSRRCI
, MASK_CSRRCI
)
862 DECLARE_INSN(fadd_s
, MATCH_FADD_S
, MASK_FADD_S
)
863 DECLARE_INSN(fsub_s
, MATCH_FSUB_S
, MASK_FSUB_S
)
864 DECLARE_INSN(fmul_s
, MATCH_FMUL_S
, MASK_FMUL_S
)
865 DECLARE_INSN(fdiv_s
, MATCH_FDIV_S
, MASK_FDIV_S
)
866 DECLARE_INSN(fsgnj_s
, MATCH_FSGNJ_S
, MASK_FSGNJ_S
)
867 DECLARE_INSN(fsgnjn_s
, MATCH_FSGNJN_S
, MASK_FSGNJN_S
)
868 DECLARE_INSN(fsgnjx_s
, MATCH_FSGNJX_S
, MASK_FSGNJX_S
)
869 DECLARE_INSN(fmin_s
, MATCH_FMIN_S
, MASK_FMIN_S
)
870 DECLARE_INSN(fmax_s
, MATCH_FMAX_S
, MASK_FMAX_S
)
871 DECLARE_INSN(fsqrt_s
, MATCH_FSQRT_S
, MASK_FSQRT_S
)
872 DECLARE_INSN(fadd_d
, MATCH_FADD_D
, MASK_FADD_D
)
873 DECLARE_INSN(fsub_d
, MATCH_FSUB_D
, MASK_FSUB_D
)
874 DECLARE_INSN(fmul_d
, MATCH_FMUL_D
, MASK_FMUL_D
)
875 DECLARE_INSN(fdiv_d
, MATCH_FDIV_D
, MASK_FDIV_D
)
876 DECLARE_INSN(fsgnj_d
, MATCH_FSGNJ_D
, MASK_FSGNJ_D
)
877 DECLARE_INSN(fsgnjn_d
, MATCH_FSGNJN_D
, MASK_FSGNJN_D
)
878 DECLARE_INSN(fsgnjx_d
, MATCH_FSGNJX_D
, MASK_FSGNJX_D
)
879 DECLARE_INSN(fmin_d
, MATCH_FMIN_D
, MASK_FMIN_D
)
880 DECLARE_INSN(fmax_d
, MATCH_FMAX_D
, MASK_FMAX_D
)
881 DECLARE_INSN(fcvt_s_d
, MATCH_FCVT_S_D
, MASK_FCVT_S_D
)
882 DECLARE_INSN(fcvt_d_s
, MATCH_FCVT_D_S
, MASK_FCVT_D_S
)
883 DECLARE_INSN(fsqrt_d
, MATCH_FSQRT_D
, MASK_FSQRT_D
)
884 DECLARE_INSN(fle_s
, MATCH_FLE_S
, MASK_FLE_S
)
885 DECLARE_INSN(flt_s
, MATCH_FLT_S
, MASK_FLT_S
)
886 DECLARE_INSN(feq_s
, MATCH_FEQ_S
, MASK_FEQ_S
)
887 DECLARE_INSN(fle_d
, MATCH_FLE_D
, MASK_FLE_D
)
888 DECLARE_INSN(flt_d
, MATCH_FLT_D
, MASK_FLT_D
)
889 DECLARE_INSN(feq_d
, MATCH_FEQ_D
, MASK_FEQ_D
)
890 DECLARE_INSN(fcvt_w_s
, MATCH_FCVT_W_S
, MASK_FCVT_W_S
)
891 DECLARE_INSN(fcvt_wu_s
, MATCH_FCVT_WU_S
, MASK_FCVT_WU_S
)
892 DECLARE_INSN(fcvt_l_s
, MATCH_FCVT_L_S
, MASK_FCVT_L_S
)
893 DECLARE_INSN(fcvt_lu_s
, MATCH_FCVT_LU_S
, MASK_FCVT_LU_S
)
894 DECLARE_INSN(fmv_x_s
, MATCH_FMV_X_S
, MASK_FMV_X_S
)
895 DECLARE_INSN(fclass_s
, MATCH_FCLASS_S
, MASK_FCLASS_S
)
896 DECLARE_INSN(fcvt_w_d
, MATCH_FCVT_W_D
, MASK_FCVT_W_D
)
897 DECLARE_INSN(fcvt_wu_d
, MATCH_FCVT_WU_D
, MASK_FCVT_WU_D
)
898 DECLARE_INSN(fcvt_l_d
, MATCH_FCVT_L_D
, MASK_FCVT_L_D
)
899 DECLARE_INSN(fcvt_lu_d
, MATCH_FCVT_LU_D
, MASK_FCVT_LU_D
)
900 DECLARE_INSN(fmv_x_d
, MATCH_FMV_X_D
, MASK_FMV_X_D
)
901 DECLARE_INSN(fclass_d
, MATCH_FCLASS_D
, MASK_FCLASS_D
)
902 DECLARE_INSN(fcvt_s_w
, MATCH_FCVT_S_W
, MASK_FCVT_S_W
)
903 DECLARE_INSN(fcvt_s_wu
, MATCH_FCVT_S_WU
, MASK_FCVT_S_WU
)
904 DECLARE_INSN(fcvt_s_l
, MATCH_FCVT_S_L
, MASK_FCVT_S_L
)
905 DECLARE_INSN(fcvt_s_lu
, MATCH_FCVT_S_LU
, MASK_FCVT_S_LU
)
906 DECLARE_INSN(fmv_s_x
, MATCH_FMV_S_X
, MASK_FMV_S_X
)
907 DECLARE_INSN(fcvt_d_w
, MATCH_FCVT_D_W
, MASK_FCVT_D_W
)
908 DECLARE_INSN(fcvt_d_wu
, MATCH_FCVT_D_WU
, MASK_FCVT_D_WU
)
909 DECLARE_INSN(fcvt_d_l
, MATCH_FCVT_D_L
, MASK_FCVT_D_L
)
910 DECLARE_INSN(fcvt_d_lu
, MATCH_FCVT_D_LU
, MASK_FCVT_D_LU
)
911 DECLARE_INSN(fmv_d_x
, MATCH_FMV_D_X
, MASK_FMV_D_X
)
912 DECLARE_INSN(flw
, MATCH_FLW
, MASK_FLW
)
913 DECLARE_INSN(fld
, MATCH_FLD
, MASK_FLD
)
914 DECLARE_INSN(fsw
, MATCH_FSW
, MASK_FSW
)
915 DECLARE_INSN(fsd
, MATCH_FSD
, MASK_FSD
)
916 DECLARE_INSN(fmadd_s
, MATCH_FMADD_S
, MASK_FMADD_S
)
917 DECLARE_INSN(fmsub_s
, MATCH_FMSUB_S
, MASK_FMSUB_S
)
918 DECLARE_INSN(fnmsub_s
, MATCH_FNMSUB_S
, MASK_FNMSUB_S
)
919 DECLARE_INSN(fnmadd_s
, MATCH_FNMADD_S
, MASK_FNMADD_S
)
920 DECLARE_INSN(fmadd_d
, MATCH_FMADD_D
, MASK_FMADD_D
)
921 DECLARE_INSN(fmsub_d
, MATCH_FMSUB_D
, MASK_FMSUB_D
)
922 DECLARE_INSN(fnmsub_d
, MATCH_FNMSUB_D
, MASK_FNMSUB_D
)
923 DECLARE_INSN(fnmadd_d
, MATCH_FNMADD_D
, MASK_FNMADD_D
)
924 DECLARE_INSN(c_nop
, MATCH_C_NOP
, MASK_C_NOP
)
925 DECLARE_INSN(c_addi16sp
, MATCH_C_ADDI16SP
, MASK_C_ADDI16SP
)
926 DECLARE_INSN(c_jr
, MATCH_C_JR
, MASK_C_JR
)
927 DECLARE_INSN(c_jalr
, MATCH_C_JALR
, MASK_C_JALR
)
928 DECLARE_INSN(c_ebreak
, MATCH_C_EBREAK
, MASK_C_EBREAK
)
929 DECLARE_INSN(c_ld
, MATCH_C_LD
, MASK_C_LD
)
930 DECLARE_INSN(c_sd
, MATCH_C_SD
, MASK_C_SD
)
931 DECLARE_INSN(c_addiw
, MATCH_C_ADDIW
, MASK_C_ADDIW
)
932 DECLARE_INSN(c_ldsp
, MATCH_C_LDSP
, MASK_C_LDSP
)
933 DECLARE_INSN(c_sdsp
, MATCH_C_SDSP
, MASK_C_SDSP
)
934 DECLARE_INSN(c_addi4spn
, MATCH_C_ADDI4SPN
, MASK_C_ADDI4SPN
)
935 DECLARE_INSN(c_fld
, MATCH_C_FLD
, MASK_C_FLD
)
936 DECLARE_INSN(c_lw
, MATCH_C_LW
, MASK_C_LW
)
937 DECLARE_INSN(c_flw
, MATCH_C_FLW
, MASK_C_FLW
)
938 DECLARE_INSN(c_fsd
, MATCH_C_FSD
, MASK_C_FSD
)
939 DECLARE_INSN(c_sw
, MATCH_C_SW
, MASK_C_SW
)
940 DECLARE_INSN(c_fsw
, MATCH_C_FSW
, MASK_C_FSW
)
941 DECLARE_INSN(c_addi
, MATCH_C_ADDI
, MASK_C_ADDI
)
942 DECLARE_INSN(c_jal
, MATCH_C_JAL
, MASK_C_JAL
)
943 DECLARE_INSN(c_li
, MATCH_C_LI
, MASK_C_LI
)
944 DECLARE_INSN(c_lui
, MATCH_C_LUI
, MASK_C_LUI
)
945 DECLARE_INSN(c_srli
, MATCH_C_SRLI
, MASK_C_SRLI
)
946 DECLARE_INSN(c_srai
, MATCH_C_SRAI
, MASK_C_SRAI
)
947 DECLARE_INSN(c_andi
, MATCH_C_ANDI
, MASK_C_ANDI
)
948 DECLARE_INSN(c_sub
, MATCH_C_SUB
, MASK_C_SUB
)
949 DECLARE_INSN(c_xor
, MATCH_C_XOR
, MASK_C_XOR
)
950 DECLARE_INSN(c_or
, MATCH_C_OR
, MASK_C_OR
)
951 DECLARE_INSN(c_and
, MATCH_C_AND
, MASK_C_AND
)
952 DECLARE_INSN(c_subw
, MATCH_C_SUBW
, MASK_C_SUBW
)
953 DECLARE_INSN(c_addw
, MATCH_C_ADDW
, MASK_C_ADDW
)
954 DECLARE_INSN(c_j
, MATCH_C_J
, MASK_C_J
)
955 DECLARE_INSN(c_beqz
, MATCH_C_BEQZ
, MASK_C_BEQZ
)
956 DECLARE_INSN(c_bnez
, MATCH_C_BNEZ
, MASK_C_BNEZ
)
957 DECLARE_INSN(c_slli
, MATCH_C_SLLI
, MASK_C_SLLI
)
958 DECLARE_INSN(c_fldsp
, MATCH_C_FLDSP
, MASK_C_FLDSP
)
959 DECLARE_INSN(c_lwsp
, MATCH_C_LWSP
, MASK_C_LWSP
)
960 DECLARE_INSN(c_flwsp
, MATCH_C_FLWSP
, MASK_C_FLWSP
)
961 DECLARE_INSN(c_mv
, MATCH_C_MV
, MASK_C_MV
)
962 DECLARE_INSN(c_add
, MATCH_C_ADD
, MASK_C_ADD
)
963 DECLARE_INSN(c_fsdsp
, MATCH_C_FSDSP
, MASK_C_FSDSP
)
964 DECLARE_INSN(c_swsp
, MATCH_C_SWSP
, MASK_C_SWSP
)
965 DECLARE_INSN(c_fswsp
, MATCH_C_FSWSP
, MASK_C_FSWSP
)
966 DECLARE_INSN(custom0
, MATCH_CUSTOM0
, MASK_CUSTOM0
)
967 DECLARE_INSN(custom0_rs1
, MATCH_CUSTOM0_RS1
, MASK_CUSTOM0_RS1
)
968 DECLARE_INSN(custom0_rs1_rs2
, MATCH_CUSTOM0_RS1_RS2
, MASK_CUSTOM0_RS1_RS2
)
969 DECLARE_INSN(custom0_rd
, MATCH_CUSTOM0_RD
, MASK_CUSTOM0_RD
)
970 DECLARE_INSN(custom0_rd_rs1
, MATCH_CUSTOM0_RD_RS1
, MASK_CUSTOM0_RD_RS1
)
971 DECLARE_INSN(custom0_rd_rs1_rs2
, MATCH_CUSTOM0_RD_RS1_RS2
, MASK_CUSTOM0_RD_RS1_RS2
)
972 DECLARE_INSN(custom1
, MATCH_CUSTOM1
, MASK_CUSTOM1
)
973 DECLARE_INSN(custom1_rs1
, MATCH_CUSTOM1_RS1
, MASK_CUSTOM1_RS1
)
974 DECLARE_INSN(custom1_rs1_rs2
, MATCH_CUSTOM1_RS1_RS2
, MASK_CUSTOM1_RS1_RS2
)
975 DECLARE_INSN(custom1_rd
, MATCH_CUSTOM1_RD
, MASK_CUSTOM1_RD
)
976 DECLARE_INSN(custom1_rd_rs1
, MATCH_CUSTOM1_RD_RS1
, MASK_CUSTOM1_RD_RS1
)
977 DECLARE_INSN(custom1_rd_rs1_rs2
, MATCH_CUSTOM1_RD_RS1_RS2
, MASK_CUSTOM1_RD_RS1_RS2
)
978 DECLARE_INSN(custom2
, MATCH_CUSTOM2
, MASK_CUSTOM2
)
979 DECLARE_INSN(custom2_rs1
, MATCH_CUSTOM2_RS1
, MASK_CUSTOM2_RS1
)
980 DECLARE_INSN(custom2_rs1_rs2
, MATCH_CUSTOM2_RS1_RS2
, MASK_CUSTOM2_RS1_RS2
)
981 DECLARE_INSN(custom2_rd
, MATCH_CUSTOM2_RD
, MASK_CUSTOM2_RD
)
982 DECLARE_INSN(custom2_rd_rs1
, MATCH_CUSTOM2_RD_RS1
, MASK_CUSTOM2_RD_RS1
)
983 DECLARE_INSN(custom2_rd_rs1_rs2
, MATCH_CUSTOM2_RD_RS1_RS2
, MASK_CUSTOM2_RD_RS1_RS2
)
984 DECLARE_INSN(custom3
, MATCH_CUSTOM3
, MASK_CUSTOM3
)
985 DECLARE_INSN(custom3_rs1
, MATCH_CUSTOM3_RS1
, MASK_CUSTOM3_RS1
)
986 DECLARE_INSN(custom3_rs1_rs2
, MATCH_CUSTOM3_RS1_RS2
, MASK_CUSTOM3_RS1_RS2
)
987 DECLARE_INSN(custom3_rd
, MATCH_CUSTOM3_RD
, MASK_CUSTOM3_RD
)
988 DECLARE_INSN(custom3_rd_rs1
, MATCH_CUSTOM3_RD_RS1
, MASK_CUSTOM3_RD_RS1
)
989 DECLARE_INSN(custom3_rd_rs1_rs2
, MATCH_CUSTOM3_RD_RS1_RS2
, MASK_CUSTOM3_RD_RS1_RS2
)
992 DECLARE_CSR(fflags
, CSR_FFLAGS
)
993 DECLARE_CSR(frm
, CSR_FRM
)
994 DECLARE_CSR(fcsr
, CSR_FCSR
)
995 DECLARE_CSR(cycle
, CSR_CYCLE
)
996 DECLARE_CSR(time
, CSR_TIME
)
997 DECLARE_CSR(instret
, CSR_INSTRET
)
998 DECLARE_CSR(sstatus
, CSR_SSTATUS
)
999 DECLARE_CSR(sie
, CSR_SIE
)
1000 DECLARE_CSR(stvec
, CSR_STVEC
)
1001 DECLARE_CSR(sscratch
, CSR_SSCRATCH
)
1002 DECLARE_CSR(sepc
, CSR_SEPC
)
1003 DECLARE_CSR(scause
, CSR_SCAUSE
)
1004 DECLARE_CSR(sbadaddr
, CSR_SBADADDR
)
1005 DECLARE_CSR(sip
, CSR_SIP
)
1006 DECLARE_CSR(sptbr
, CSR_SPTBR
)
1007 DECLARE_CSR(scycle
, CSR_SCYCLE
)
1008 DECLARE_CSR(stime
, CSR_STIME
)
1009 DECLARE_CSR(sinstret
, CSR_SINSTRET
)
1010 DECLARE_CSR(mstatus
, CSR_MSTATUS
)
1011 DECLARE_CSR(medeleg
, CSR_MEDELEG
)
1012 DECLARE_CSR(mideleg
, CSR_MIDELEG
)
1013 DECLARE_CSR(mie
, CSR_MIE
)
1014 DECLARE_CSR(mtvec
, CSR_MTVEC
)
1015 DECLARE_CSR(mscratch
, CSR_MSCRATCH
)
1016 DECLARE_CSR(mepc
, CSR_MEPC
)
1017 DECLARE_CSR(mcause
, CSR_MCAUSE
)
1018 DECLARE_CSR(mbadaddr
, CSR_MBADADDR
)
1019 DECLARE_CSR(mip
, CSR_MIP
)
1020 DECLARE_CSR(mucounteren
, CSR_MUCOUNTEREN
)
1021 DECLARE_CSR(mscounteren
, CSR_MSCOUNTEREN
)
1022 DECLARE_CSR(mucycle_delta
, CSR_MUCYCLE_DELTA
)
1023 DECLARE_CSR(mutime_delta
, CSR_MUTIME_DELTA
)
1024 DECLARE_CSR(muinstret_delta
, CSR_MUINSTRET_DELTA
)
1025 DECLARE_CSR(mscycle_delta
, CSR_MSCYCLE_DELTA
)
1026 DECLARE_CSR(mstime_delta
, CSR_MSTIME_DELTA
)
1027 DECLARE_CSR(msinstret_delta
, CSR_MSINSTRET_DELTA
)
1028 DECLARE_CSR(tselect
, CSR_TSELECT
)
1029 DECLARE_CSR(tdata0
, CSR_TDATA0
)
1030 DECLARE_CSR(tdata1
, CSR_TDATA1
)
1031 DECLARE_CSR(tdata2
, CSR_TDATA2
)
1032 DECLARE_CSR(dcsr
, CSR_DCSR
)
1033 DECLARE_CSR(dpc
, CSR_DPC
)
1034 DECLARE_CSR(dscratch
, CSR_DSCRATCH
)
1035 DECLARE_CSR(mcycle
, CSR_MCYCLE
)
1036 DECLARE_CSR(mtime
, CSR_MTIME
)
1037 DECLARE_CSR(minstret
, CSR_MINSTRET
)
1038 DECLARE_CSR(misa
, CSR_MISA
)
1039 DECLARE_CSR(mvendorid
, CSR_MVENDORID
)
1040 DECLARE_CSR(marchid
, CSR_MARCHID
)
1041 DECLARE_CSR(mimpid
, CSR_MIMPID
)
1042 DECLARE_CSR(mhartid
, CSR_MHARTID
)
1043 DECLARE_CSR(mreset
, CSR_MRESET
)
1044 DECLARE_CSR(cycleh
, CSR_CYCLEH
)
1045 DECLARE_CSR(timeh
, CSR_TIMEH
)
1046 DECLARE_CSR(instreth
, CSR_INSTRETH
)
1047 DECLARE_CSR(mucycle_deltah
, CSR_MUCYCLE_DELTAH
)
1048 DECLARE_CSR(mutime_deltah
, CSR_MUTIME_DELTAH
)
1049 DECLARE_CSR(muinstret_deltah
, CSR_MUINSTRET_DELTAH
)
1050 DECLARE_CSR(mscycle_deltah
, CSR_MSCYCLE_DELTAH
)
1051 DECLARE_CSR(mstime_deltah
, CSR_MSTIME_DELTAH
)
1052 DECLARE_CSR(msinstret_deltah
, CSR_MSINSTRET_DELTAH
)
1053 DECLARE_CSR(mcycleh
, CSR_MCYCLEH
)
1054 DECLARE_CSR(mtimeh
, CSR_MTIMEH
)
1055 DECLARE_CSR(minstreth
, CSR_MINSTRETH
)
1057 #ifdef DECLARE_CAUSE
1058 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH
)
1059 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH
)
1060 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION
)
1061 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT
)
1062 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD
)
1063 DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD
)
1064 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE
)
1065 DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE
)
1066 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL
)
1067 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL
)
1068 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL
)
1069 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL
)