6 #include <sys/socket.h>
18 #include "gdbserver.h"
22 //////////////////////////////////////// Utility Functions
31 void die(const char* msg
)
33 fprintf(stderr
, "gdbserver code died: %s\n", msg
);
37 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
38 // its source tree. We must interpret the numbers the same here.
46 REG_MSTATUS
= CSR_MSTATUS
+ REG_CSR0
,
51 //////////////////////////////////////// Functions to generate RISC-V opcodes.
53 // TODO: Does this already exist somewhere?
56 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
57 // spec says it should be 2 and 3.
60 static uint32_t bits(uint32_t value
, unsigned int hi
, unsigned int lo
) {
61 return (value
>> lo
) & ((1 << (hi
+1-lo
)) - 1);
64 static uint32_t bit(uint32_t value
, unsigned int b
) {
65 return (value
>> b
) & 1;
68 static uint32_t jal(unsigned int rd
, uint32_t imm
) {
69 return (bit(imm
, 20) << 31) |
70 (bits(imm
, 10, 1) << 21) |
71 (bit(imm
, 11) << 20) |
72 (bits(imm
, 19, 12) << 12) |
77 static uint32_t csrsi(unsigned int csr
, uint16_t imm
) {
79 (bits(imm
, 4, 0) << 15) |
83 static uint32_t csrci(unsigned int csr
, uint16_t imm
) {
85 (bits(imm
, 4, 0) << 15) |
89 static uint32_t csrr(unsigned int rd
, unsigned int csr
) {
90 return (csr
<< 20) | (rd
<< 7) | MATCH_CSRRS
;
93 static uint32_t csrw(unsigned int source
, unsigned int csr
) {
94 return (csr
<< 20) | (source
<< 15) | MATCH_CSRRW
;
97 static uint32_t fence_i()
102 static uint32_t sb(unsigned int src
, unsigned int base
, uint16_t offset
)
104 return (bits(offset
, 11, 5) << 25) |
107 (bits(offset
, 4, 0) << 7) |
111 static uint32_t sh(unsigned int src
, unsigned int base
, uint16_t offset
)
113 return (bits(offset
, 11, 5) << 25) |
116 (bits(offset
, 4, 0) << 7) |
120 static uint32_t sw(unsigned int src
, unsigned int base
, uint16_t offset
)
122 return (bits(offset
, 11, 5) << 25) |
125 (bits(offset
, 4, 0) << 7) |
129 static uint32_t sd(unsigned int src
, unsigned int base
, uint16_t offset
)
131 return (bits(offset
, 11, 5) << 25) |
132 (bits(src
, 4, 0) << 20) |
134 (bits(offset
, 4, 0) << 7) |
138 static uint32_t sq(unsigned int src
, unsigned int base
, uint16_t offset
)
141 return (bits(offset
, 11, 5) << 25) |
142 (bits(src
, 4, 0) << 20) |
144 (bits(offset
, 4, 0) << 7) |
151 static uint32_t lq(unsigned int rd
, unsigned int base
, uint16_t offset
)
154 return (bits(offset
, 11, 0) << 20) |
156 (bits(rd
, 4, 0) << 7) |
163 static uint32_t ld(unsigned int rd
, unsigned int base
, uint16_t offset
)
165 return (bits(offset
, 11, 0) << 20) |
167 (bits(rd
, 4, 0) << 7) |
171 static uint32_t lw(unsigned int rd
, unsigned int base
, uint16_t offset
)
173 return (bits(offset
, 11, 0) << 20) |
175 (bits(rd
, 4, 0) << 7) |
179 static uint32_t lh(unsigned int rd
, unsigned int base
, uint16_t offset
)
181 return (bits(offset
, 11, 0) << 20) |
183 (bits(rd
, 4, 0) << 7) |
187 static uint32_t lb(unsigned int rd
, unsigned int base
, uint16_t offset
)
189 return (bits(offset
, 11, 0) << 20) |
191 (bits(rd
, 4, 0) << 7) |
195 static uint32_t fsw(unsigned int src
, unsigned int base
, uint16_t offset
)
197 return (bits(offset
, 11, 5) << 25) |
198 (bits(src
, 4, 0) << 20) |
200 (bits(offset
, 4, 0) << 7) |
204 static uint32_t fsd(unsigned int src
, unsigned int base
, uint16_t offset
)
206 return (bits(offset
, 11, 5) << 25) |
207 (bits(src
, 4, 0) << 20) |
209 (bits(offset
, 4, 0) << 7) |
213 static uint32_t flw(unsigned int dest
, unsigned int base
, uint16_t offset
)
215 return (bits(offset
, 11, 0) << 20) |
217 (bits(dest
, 4, 0) << 7) |
221 static uint32_t fld(unsigned int dest
, unsigned int base
, uint16_t offset
)
223 return (bits(offset
, 11, 0) << 20) |
225 (bits(dest
, 4, 0) << 7) |
229 static uint32_t addi(unsigned int dest
, unsigned int src
, uint16_t imm
)
231 return (bits(imm
, 11, 0) << 20) |
237 static uint32_t ori(unsigned int dest
, unsigned int src
, uint16_t imm
)
239 return (bits(imm
, 11, 0) << 20) |
245 static uint32_t xori(unsigned int dest
, unsigned int src
, uint16_t imm
)
247 return (bits(imm
, 11, 0) << 20) |
253 static uint32_t srli(unsigned int dest
, unsigned int src
, uint8_t shamt
)
255 return (bits(shamt
, 4, 0) << 20) |
262 static uint32_t nop()
264 return addi(0, 0, 0);
267 template <typename T
>
268 unsigned int circular_buffer_t
<T
>::size() const
273 return end
+ capacity
- start
;
276 template <typename T
>
277 void circular_buffer_t
<T
>::consume(unsigned int bytes
)
279 start
= (start
+ bytes
) % capacity
;
282 template <typename T
>
283 unsigned int circular_buffer_t
<T
>::contiguous_empty_size() const
287 return capacity
- end
- 1;
289 return capacity
- end
;
291 return start
- end
- 1;
294 template <typename T
>
295 unsigned int circular_buffer_t
<T
>::contiguous_data_size() const
300 return capacity
- start
;
303 template <typename T
>
304 void circular_buffer_t
<T
>::data_added(unsigned int bytes
)
307 assert(end
<= capacity
);
312 template <typename T
>
313 void circular_buffer_t
<T
>::reset()
319 template <typename T
>
320 void circular_buffer_t
<T
>::append(const T
*src
, unsigned int count
)
322 unsigned int copy
= std::min(count
, contiguous_empty_size());
323 memcpy(contiguous_empty(), src
, copy
* sizeof(T
));
327 assert(count
< contiguous_empty_size());
328 memcpy(contiguous_empty(), src
+copy
, count
* sizeof(T
));
333 ////////////////////////////// Debug Operations
335 class halt_op_t
: public operation_t
338 halt_op_t(gdbserver_t
& gdbserver
, bool send_status
=false) :
339 operation_t(gdbserver
), send_status(send_status
),
342 void write_dpc_program() {
343 gs
.dr_write32(0, csrsi(CSR_DCSR
, DCSR_HALT
));
344 gs
.dr_write32(1, csrr(S0
, CSR_DPC
));
345 gs
.dr_write_store(2, S0
, SLOT_DATA0
);
350 bool perform_step(unsigned int step
) {
352 gs
.tselect_valid
= false;
355 gs
.dr_write32(0, xori(S1
, ZERO
, -1));
356 gs
.dr_write32(1, srli(S1
, S1
, 31));
357 // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
358 gs
.dr_write32(2, sw(S1
, ZERO
, DEBUG_RAM_START
));
359 gs
.dr_write32(3, srli(S1
, S1
, 31));
360 // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
361 gs
.dr_write32(4, sw(S1
, ZERO
, DEBUG_RAM_START
+ 4));
374 uint32_t word0
= gs
.dr_read32(0);
375 uint32_t word1
= gs
.dr_read32(1);
377 if (word0
== 1 && word1
== 0) {
379 } else if (word0
== 0xffffffff && word1
== 3) {
381 } else if (word0
== 0xffffffff && word1
== 0xffffffff) {
391 gs
.dpc
= gs
.dr_read(SLOT_DATA0
);
392 gs
.dr_write32(0, csrr(S0
, CSR_MSTATUS
));
393 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
400 gs
.mstatus
= gs
.dr_read(SLOT_DATA0
);
401 gs
.mstatus_dirty
= false;
402 gs
.dr_write32(0, csrr(S0
, CSR_DCSR
));
403 gs
.dr_write32(1, sw(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
410 gs
.dcsr
= gs
.dr_read32(4);
412 gs
.sptbr_valid
= false;
413 gs
.pte_cache
.clear();
416 switch (get_field(gs
.dcsr
, DCSR_CAUSE
)) {
417 case DCSR_CAUSE_NONE
:
418 fprintf(stderr
, "Internal error. Processor halted without reason.\n");
421 case DCSR_CAUSE_DEBUGINT
:
422 gs
.send_packet("S02"); // Pretend program received SIGINT.
425 case DCSR_CAUSE_HWBP
:
426 case DCSR_CAUSE_STEP
:
427 case DCSR_CAUSE_HALT
:
428 // There's no gdb code for this.
429 gs
.send_packet("T05");
431 case DCSR_CAUSE_SWBP
:
432 gs
.send_packet("T05swbreak:;");
455 class continue_op_t
: public operation_t
458 continue_op_t(gdbserver_t
& gdbserver
, bool single_step
) :
459 operation_t(gdbserver
), single_step(single_step
) {};
461 bool perform_step(unsigned int step
) {
462 D(fprintf(stderr
, "continue step %d\n", step
));
465 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
466 gs
.dr_write32(1, csrw(S0
, CSR_DPC
));
467 // TODO: Isn't there a fence.i in Debug ROM already?
468 if (gs
.fence_i_required
) {
469 gs
.dr_write32(2, fence_i());
471 gs
.fence_i_required
= false;
475 gs
.dr_write(SLOT_DATA0
, gs
.dpc
);
480 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
481 gs
.dr_write32(1, csrw(S0
, CSR_MSTATUS
));
483 gs
.dr_write(SLOT_DATA0
, gs
.mstatus
);
488 gs
.dr_write32(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+16));
489 gs
.dr_write32(1, csrw(S0
, CSR_DCSR
));
492 reg_t dcsr
= set_field(gs
.dcsr
, DCSR_HALT
, 0);
493 dcsr
= set_field(dcsr
, DCSR_STEP
, single_step
);
494 // Software breakpoints should go here.
495 dcsr
= set_field(dcsr
, DCSR_EBREAKM
, 1);
496 dcsr
= set_field(dcsr
, DCSR_EBREAKH
, 1);
497 dcsr
= set_field(dcsr
, DCSR_EBREAKS
, 1);
498 dcsr
= set_field(dcsr
, DCSR_EBREAKU
, 1);
499 gs
.dr_write32(4, dcsr
);
511 class general_registers_read_op_t
: public operation_t
513 // Register order that gdb expects is:
514 // "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
515 // "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
516 // "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
517 // "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
519 // Each byte of register data is described by two hex digits. The bytes with
520 // the register are transmitted in target byte order. The size of each
521 // register and their position within the ‘g’ packet are determined by the
522 // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
523 // gdbarch_register_name.
526 general_registers_read_op_t(gdbserver_t
& gdbserver
) :
527 operation_t(gdbserver
) {};
529 bool perform_step(unsigned int step
)
531 D(fprintf(stderr
, "register_read step %d\n", step
));
535 // x0 is always zero.
537 gs
.send((uint32_t) 0);
539 gs
.send((uint64_t) 0);
542 gs
.dr_write_store(0, 1, SLOT_DATA0
);
543 gs
.dr_write_store(1, 2, SLOT_DATA1
);
550 gs
.send((uint32_t) gs
.dr_read(SLOT_DATA0
));
552 gs
.send((uint64_t) gs
.dr_read(SLOT_DATA0
));
560 gs
.send((uint32_t) gs
.dr_read(SLOT_DATA1
));
562 gs
.send((uint64_t) gs
.dr_read(SLOT_DATA1
));
565 unsigned int current_reg
= 2 * step
+ 1;
567 if (current_reg
== S1
) {
568 gs
.dr_write_load(i
++, S1
, SLOT_DATA_LAST
);
570 gs
.dr_write_store(i
++, current_reg
, SLOT_DATA0
);
571 if (current_reg
+ 1 == S0
) {
572 gs
.dr_write32(i
++, csrr(S0
, CSR_DSCRATCH
));
575 gs
.dr_write_store(i
++, current_reg
+1, SLOT_DATA1
);
584 class register_read_op_t
: public operation_t
587 register_read_op_t(gdbserver_t
& gdbserver
, unsigned int reg
) :
588 operation_t(gdbserver
), reg(reg
) {};
590 bool perform_step(unsigned int step
)
594 if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
597 gs
.dr_write32(i
++, csrr(S0
, CSR_DSCRATCH
));
600 gs
.dr_write32(i
++, sw(reg
- REG_XPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
602 gs
.dr_write32(i
++, sd(reg
- REG_XPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
605 } else if (reg
== REG_PC
) {
608 gs
.send((uint32_t) gs
.dpc
);
614 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
615 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
616 gs
.dr_write(SLOT_DATA1
, set_field(gs
.mstatus
, MSTATUS_FS
, 1));
617 gs
.dr_write32(1, csrw(S0
, CSR_MSTATUS
));
618 gs
.mstatus_dirty
= true;
620 gs
.dr_write32(2, fsw(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
622 gs
.dr_write32(2, fsd(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
625 } else if (reg
== REG_MSTATUS
) {
628 gs
.send((uint32_t) gs
.mstatus
);
634 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
635 gs
.dr_write32(0, csrr(S0
, reg
- REG_CSR0
));
636 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
638 // If we hit an exception reading the CSR, we'll end up returning ~0 as
639 // the register's value, which is what we want. (Right?)
640 gs
.dr_write(SLOT_DATA0
, ~(uint64_t) 0);
641 } else if (reg
== REG_PRIV
) {
643 gs
.send((uint8_t) get_field(gs
.dcsr
, DCSR_PRV
));
647 gs
.send_packet("E02");
655 unsigned result
= gs
.dr_read32(DEBUG_RAM_SIZE
/ 4 - 1);
657 gs
.send_packet("E03");
662 gs
.send(gs
.dr_read32(4));
664 gs
.send(gs
.dr_read(SLOT_DATA0
));
677 class register_write_op_t
: public operation_t
680 register_write_op_t(gdbserver_t
& gdbserver
, unsigned int reg
, reg_t value
) :
681 operation_t(gdbserver
), reg(reg
), value(value
) {};
683 bool perform_step(unsigned int step
)
687 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
688 gs
.dr_write(SLOT_DATA0
, value
);
690 gs
.dr_write32(1, csrw(S0
, CSR_DSCRATCH
));
692 } else if (reg
== S1
) {
693 gs
.dr_write_store(1, S0
, SLOT_DATA_LAST
);
695 } else if (reg
>= REG_XPR0
&& reg
<= REG_XPR31
) {
696 gs
.dr_write32(1, addi(reg
, S0
, 0));
698 } else if (reg
== REG_PC
) {
701 } else if (reg
>= REG_FPR0
&& reg
<= REG_FPR31
) {
702 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
703 gs
.dr_write(SLOT_DATA1
, set_field(gs
.mstatus
, MSTATUS_FS
, 1));
704 gs
.dr_write32(1, csrw(S0
, CSR_MSTATUS
));
705 gs
.mstatus_dirty
= true;
707 gs
.dr_write32(2, flw(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
709 gs
.dr_write32(2, fld(reg
- REG_FPR0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
712 } else if (reg
== REG_MSTATUS
) {
714 gs
.mstatus_dirty
= true;
716 } else if (reg
>= REG_CSR0
&& reg
<= REG_CSR4095
) {
717 gs
.dr_write32(1, csrw(S0
, reg
- REG_CSR0
));
719 if (reg
== REG_CSR0
+ CSR_SPTBR
) {
721 gs
.sptbr_valid
= true;
723 } else if (reg
== REG_PRIV
) {
724 gs
.dcsr
= set_field(gs
.dcsr
, DCSR_PRV
, value
);
727 gs
.send_packet("E02");
735 unsigned result
= gs
.dr_read32(DEBUG_RAM_SIZE
/ 4 - 1);
737 gs
.send_packet("E03");
740 gs
.send_packet("OK");
753 class memory_read_op_t
: public operation_t
756 // Read length bytes from vaddr, storing the result into data.
757 // If data is NULL, send the result straight to gdb.
758 memory_read_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
759 unsigned char *data
=NULL
) :
760 operation_t(gdbserver
), vaddr(vaddr
), length(length
), data(data
), index(0)
762 buf
= new uint8_t[length
];
770 bool perform_step(unsigned int step
)
773 // address goes in S0
774 paddr
= gs
.translate(vaddr
);
775 access_size
= gs
.find_access_size(paddr
, length
);
777 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
778 switch (access_size
) {
780 gs
.dr_write32(1, lb(S1
, S0
, 0));
783 gs
.dr_write32(1, lh(S1
, S0
, 0));
786 gs
.dr_write32(1, lw(S1
, S0
, 0));
789 gs
.dr_write32(1, ld(S1
, S0
, 0));
792 gs
.dr_write_store(2, S1
, SLOT_DATA1
);
794 gs
.dr_write(SLOT_DATA0
, paddr
);
800 if (gs
.dr_read32(DEBUG_RAM_SIZE
/ 4 - 1)) {
801 // Note that OpenOCD doesn't report this error to gdb by default. They
802 // think it can mess up stack tracing. So far I haven't seen any
804 gs
.send_packet("E99");
808 reg_t value
= gs
.dr_read(SLOT_DATA1
);
809 for (unsigned int i
= 0; i
< access_size
; i
++) {
811 *(data
++) = value
& 0xff;
812 D(fprintf(stderr
, "%02x", (unsigned int) (value
& 0xff)));
814 buf
[index
++] = value
& 0xff;
819 D(fprintf(stderr
, "\n"));
821 length
-= access_size
;
822 paddr
+= access_size
;
828 for (unsigned int i
= 0; i
< index
; i
++) {
829 sprintf(buffer
, "%02x", (unsigned int) buf
[i
]);
836 gs
.dr_write(SLOT_DATA0
, paddr
);
847 unsigned int access_size
;
852 class memory_write_op_t
: public operation_t
855 memory_write_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, unsigned int length
,
856 const unsigned char *data
) :
857 operation_t(gdbserver
), vaddr(vaddr
), offset(0), length(length
), data(data
) {};
859 ~memory_write_op_t() {
863 bool perform_step(unsigned int step
)
865 reg_t paddr
= gs
.translate(vaddr
);
867 unsigned int data_offset
;
870 data_offset
= slot_offset32
[SLOT_DATA1
];
873 data_offset
= slot_offset64
[SLOT_DATA1
];
876 data_offset
= slot_offset128
[SLOT_DATA1
];
883 access_size
= gs
.find_access_size(paddr
, length
);
885 D(fprintf(stderr
, "write to 0x%" PRIx64
" -> 0x%" PRIx64
" (access=%d): ",
886 vaddr
, paddr
, access_size
));
887 for (unsigned int i
= 0; i
< length
; i
++) {
888 D(fprintf(stderr
, "%02x", data
[i
]));
890 D(fprintf(stderr
, "\n"));
892 // address goes in S0
893 gs
.dr_write_load(0, S0
, SLOT_DATA0
);
894 switch (access_size
) {
896 gs
.dr_write32(1, lb(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
897 gs
.dr_write32(2, sb(S1
, S0
, 0));
898 gs
.dr_write32(data_offset
, data
[0]);
901 gs
.dr_write32(1, lh(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
902 gs
.dr_write32(2, sh(S1
, S0
, 0));
903 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8));
906 gs
.dr_write32(1, lw(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
907 gs
.dr_write32(2, sw(S1
, S0
, 0));
908 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8) |
909 (data
[2] << 16) | (data
[3] << 24));
912 gs
.dr_write32(1, ld(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 4*data_offset
));
913 gs
.dr_write32(2, sd(S1
, S0
, 0));
914 gs
.dr_write32(data_offset
, data
[0] | (data
[1] << 8) |
915 (data
[2] << 16) | (data
[3] << 24));
916 gs
.dr_write32(data_offset
+1, data
[4] | (data
[5] << 8) |
917 (data
[6] << 16) | (data
[7] << 24));
920 fprintf(stderr
, "gdbserver error: write %d bytes to 0x%016" PRIx64
921 " -> 0x%016" PRIx64
"; access_size=%d\n",
922 length
, vaddr
, paddr
, access_size
);
923 gs
.send_packet("E12");
927 gs
.dr_write(SLOT_DATA0
, paddr
);
933 if (gs
.dr_read32(DEBUG_RAM_SIZE
/ 4 - 1)) {
934 gs
.send_packet("E98");
938 offset
+= access_size
;
939 if (offset
>= length
) {
940 gs
.send_packet("OK");
943 const unsigned char *d
= data
+ offset
;
944 switch (access_size
) {
946 gs
.dr_write32(data_offset
, d
[0]);
949 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8));
952 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8) |
953 (d
[2] << 16) | (d
[3] << 24));
956 gs
.dr_write32(data_offset
, d
[0] | (d
[1] << 8) |
957 (d
[2] << 16) | (d
[3] << 24));
958 gs
.dr_write32(data_offset
+1, d
[4] | (d
[5] << 8) |
959 (d
[6] << 16) | (d
[7] << 24));
962 gs
.send_packet("E13");
965 gs
.dr_write(SLOT_DATA0
, paddr
+ offset
);
975 unsigned int access_size
;
976 const unsigned char *data
;
979 class collect_translation_info_op_t
: public operation_t
982 // Read sufficient information from the target into gdbserver structures so
983 // that it's possible to translate vaddr, vaddr+length, and all addresses
984 // in between to physical addresses.
985 collect_translation_info_op_t(gdbserver_t
& gdbserver
, reg_t vaddr
, size_t length
) :
986 operation_t(gdbserver
), state(STATE_START
), vaddr(vaddr
), length(length
) {};
988 bool perform_step(unsigned int step
)
990 // Perform any reads from the just-completed action.
994 case STATE_READ_SPTBR
:
995 gs
.sptbr
= gs
.dr_read(SLOT_DATA0
);
996 gs
.sptbr_valid
= true;
997 vm
= decode_vm_info(gs
.xlen
, gs
.privilege_mode(), gs
.sptbr
);
1001 case STATE_READ_PTE
:
1002 if (vm
.ptesize
== 4) {
1003 gs
.pte_cache
[pte_addr
] = gs
.dr_read32(4);
1005 gs
.pte_cache
[pte_addr
] = ((uint64_t) gs
.dr_read32(5) << 32) |
1008 D(fprintf(stderr
, "pte_cache[0x%" PRIx64
"] = 0x%" PRIx64
"\n", pte_addr
,
1009 gs
.pte_cache
[pte_addr
]));
1013 // Set up the next action.
1014 // We only get here for VM_SV32/39/38.
1016 if (!gs
.sptbr_valid
) {
1017 state
= STATE_READ_SPTBR
;
1018 gs
.dr_write32(0, csrr(S0
, CSR_SPTBR
));
1019 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1020 gs
.dr_write_jump(2);
1021 gs
.set_interrupt(0);
1025 reg_t base
= vm
.ptbase
;
1026 for (int i
= vm
.levels
- 1; i
>= 0; i
--) {
1027 int ptshift
= i
* vm
.idxbits
;
1028 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << vm
.idxbits
) - 1);
1030 pte_addr
= base
+ idx
* vm
.ptesize
;
1031 auto it
= gs
.pte_cache
.find(pte_addr
);
1032 if (it
== gs
.pte_cache
.end()) {
1033 state
= STATE_READ_PTE
;
1034 if (vm
.ptesize
== 4) {
1035 gs
.dr_write32(0, lw(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1036 gs
.dr_write32(1, lw(S1
, S0
, 0));
1037 gs
.dr_write32(2, sw(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1039 assert(gs
.xlen
>= 64);
1040 gs
.dr_write32(0, ld(S0
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1041 gs
.dr_write32(1, ld(S1
, S0
, 0));
1042 gs
.dr_write32(2, sd(S1
, 0, (uint16_t) DEBUG_RAM_START
+ 16));
1044 gs
.dr_write_jump(3);
1045 gs
.dr_write32(4, pte_addr
);
1046 gs
.dr_write32(5, pte_addr
>> 32);
1047 gs
.set_interrupt(0);
1051 reg_t pte
= gs
.pte_cache
[pte_addr
];
1052 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
1054 if (PTE_TABLE(pte
)) { // next level of page table
1055 base
= ppn
<< PGSHIFT
;
1057 // We've collected all the data required for the translation.
1062 "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%016" PRIx64
"\n",
1079 class hardware_breakpoint_insert_op_t
: public operation_t
1082 hardware_breakpoint_insert_op_t(gdbserver_t
& gdbserver
,
1083 hardware_breakpoint_t bp
) :
1084 operation_t(gdbserver
), state(STATE_START
), bp(bp
) {};
1086 void write_new_index_program()
1088 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1089 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1090 gs
.dr_write32(2, csrr(S0
, CSR_TSELECT
));
1091 gs
.dr_write_store(3, S0
, SLOT_DATA1
);
1092 gs
.dr_write_jump(4);
1093 gs
.dr_write(SLOT_DATA1
, bp
.index
);
1096 bool perform_step(unsigned int step
)
1101 write_new_index_program();
1102 state
= STATE_CHECK_INDEX
;
1105 case STATE_CHECK_INDEX
:
1106 if (gs
.dr_read(SLOT_DATA1
) != bp
.index
) {
1107 // We've exhausted breakpoints without finding an appropriate one.
1108 gs
.send_packet("E58");
1112 gs
.dr_write32(0, csrr(S0
, CSR_TDATA1
));
1113 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1114 gs
.dr_write_jump(2);
1115 state
= STATE_CHECK_MCONTROL
;
1118 case STATE_CHECK_MCONTROL
:
1120 reg_t mcontrol
= gs
.dr_read(SLOT_DATA0
);
1121 unsigned int type
= mcontrol
>> (gs
.xlen
- 4);
1123 // We've exhausted breakpoints without finding an appropriate one.
1124 gs
.send_packet("E58");
1129 !get_field(mcontrol
, MCONTROL_EXECUTE
) &&
1130 !get_field(mcontrol
, MCONTROL_LOAD
) &&
1131 !get_field(mcontrol
, MCONTROL_STORE
)) {
1132 // Found an unused trigger.
1133 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1134 gs
.dr_write32(1, csrw(S0
, CSR_TDATA1
));
1135 gs
.dr_write_jump(2);
1136 mcontrol
= set_field(0, MCONTROL_ACTION
, MCONTROL_ACTION_DEBUG_MODE
);
1137 mcontrol
= set_field(mcontrol
, MCONTROL_DMODE(gs
.xlen
), 1);
1138 mcontrol
= set_field(mcontrol
, MCONTROL_MATCH
, MCONTROL_MATCH_EQUAL
);
1139 mcontrol
= set_field(mcontrol
, MCONTROL_M
, 1);
1140 mcontrol
= set_field(mcontrol
, MCONTROL_H
, 1);
1141 mcontrol
= set_field(mcontrol
, MCONTROL_S
, 1);
1142 mcontrol
= set_field(mcontrol
, MCONTROL_U
, 1);
1143 mcontrol
= set_field(mcontrol
, MCONTROL_EXECUTE
, bp
.execute
);
1144 mcontrol
= set_field(mcontrol
, MCONTROL_LOAD
, bp
.load
);
1145 mcontrol
= set_field(mcontrol
, MCONTROL_STORE
, bp
.store
);
1146 // For store triggers it's nicer to fire just before the
1147 // instruction than just after. However, gdb doesn't clear the
1148 // breakpoints and step before resuming from a store trigger.
1149 // That means that without extra code, you'll keep hitting the
1150 // same watchpoint over and over again. That's not useful at all.
1151 // Instead of fixing this the right way, just set timing=1 for
1153 if (bp
.load
|| bp
.store
)
1154 mcontrol
= set_field(mcontrol
, MCONTROL_TIMING
, 1);
1156 gs
.dr_write(SLOT_DATA1
, mcontrol
);
1157 state
= STATE_WRITE_ADDRESS
;
1160 write_new_index_program();
1161 state
= STATE_CHECK_INDEX
;
1166 case STATE_WRITE_ADDRESS
:
1168 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1169 gs
.dr_write32(1, csrw(S0
, CSR_TDATA2
));
1170 gs
.dr_write_jump(2);
1171 gs
.dr_write(SLOT_DATA1
, bp
.vaddr
);
1172 gs
.set_interrupt(0);
1173 gs
.send_packet("OK");
1175 gs
.hardware_breakpoints
.insert(bp
);
1181 gs
.set_interrupt(0);
1189 STATE_CHECK_MCONTROL
,
1192 hardware_breakpoint_t bp
;
1195 class maybe_save_tselect_op_t
: public operation_t
1198 maybe_save_tselect_op_t(gdbserver_t
& gdbserver
) : operation_t(gdbserver
) {};
1199 bool perform_step(unsigned int step
) {
1200 if (gs
.tselect_valid
)
1205 gs
.dr_write32(0, csrr(S0
, CSR_TDATA1
));
1206 gs
.dr_write_store(1, S0
, SLOT_DATA0
);
1207 gs
.dr_write_jump(2);
1208 gs
.set_interrupt(0);
1211 gs
.tselect
= gs
.dr_read(SLOT_DATA0
);
1212 gs
.tselect_valid
= true;
1219 class maybe_restore_tselect_op_t
: public operation_t
1222 maybe_restore_tselect_op_t(gdbserver_t
& gdbserver
) : operation_t(gdbserver
) {};
1223 bool perform_step(unsigned int step
) {
1224 if (gs
.tselect_valid
) {
1225 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1226 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1227 gs
.dr_write_jump(2);
1228 gs
.dr_write(SLOT_DATA1
, gs
.tselect
);
1234 class maybe_restore_mstatus_op_t
: public operation_t
1237 maybe_restore_mstatus_op_t(gdbserver_t
& gdbserver
) : operation_t(gdbserver
) {};
1238 bool perform_step(unsigned int step
) {
1239 if (gs
.mstatus_dirty
) {
1240 gs
.dr_write_load(0, S0
, SLOT_DATA1
);
1241 gs
.dr_write32(1, csrw(S0
, CSR_MSTATUS
));
1242 gs
.dr_write_jump(2);
1243 gs
.dr_write(SLOT_DATA1
, gs
.mstatus
);
1249 class hardware_breakpoint_remove_op_t
: public operation_t
1252 hardware_breakpoint_remove_op_t(gdbserver_t
& gdbserver
,
1253 hardware_breakpoint_t bp
) :
1254 operation_t(gdbserver
), bp(bp
) {};
1256 bool perform_step(unsigned int step
) {
1257 gs
.dr_write32(0, addi(S0
, ZERO
, bp
.index
));
1258 gs
.dr_write32(1, csrw(S0
, CSR_TSELECT
));
1259 gs
.dr_write32(2, csrw(ZERO
, CSR_TDATA1
));
1260 gs
.dr_write_jump(3);
1261 gs
.set_interrupt(0);
1266 hardware_breakpoint_t bp
;
1269 ////////////////////////////// gdbserver itself
1271 gdbserver_t::gdbserver_t(uint16_t port
, sim_t
*sim
) :
1275 // gdb likes to send 0x100000 bytes at once when downloading.
1276 recv_buf(0x180000), send_buf(64 * 1024)
1278 socket_fd
= socket(AF_INET
, SOCK_STREAM
, 0);
1279 if (socket_fd
== -1) {
1280 fprintf(stderr
, "failed to make socket: %s (%d)\n", strerror(errno
), errno
);
1284 fcntl(socket_fd
, F_SETFL
, O_NONBLOCK
);
1286 if (setsockopt(socket_fd
, SOL_SOCKET
, SO_REUSEADDR
, &reuseaddr
,
1287 sizeof(int)) == -1) {
1288 fprintf(stderr
, "failed setsockopt: %s (%d)\n", strerror(errno
), errno
);
1292 struct sockaddr_in addr
;
1293 memset(&addr
, 0, sizeof(addr
));
1294 addr
.sin_family
= AF_INET
;
1295 addr
.sin_addr
.s_addr
= INADDR_ANY
;
1296 addr
.sin_port
= htons(port
);
1298 if (bind(socket_fd
, (struct sockaddr
*) &addr
, sizeof(addr
)) == -1) {
1299 fprintf(stderr
, "failed to bind socket: %s (%d)\n", strerror(errno
), errno
);
1303 if (listen(socket_fd
, 1) == -1) {
1304 fprintf(stderr
, "failed to listen on socket: %s (%d)\n", strerror(errno
), errno
);
1309 unsigned int gdbserver_t::find_access_size(reg_t address
, int length
)
1311 reg_t composite
= address
| length
;
1312 if ((composite
& 0x7) == 0 && xlen
>= 64)
1314 if ((composite
& 0x3) == 0)
1319 reg_t
gdbserver_t::translate(reg_t vaddr
)
1321 vm_info vm
= decode_vm_info(xlen
, privilege_mode(), sptbr
);
1325 // Handle page tables here. There's a bunch of duplicated code with
1326 // collect_translation_info_op_t. :-(
1327 reg_t base
= vm
.ptbase
;
1328 for (int i
= vm
.levels
- 1; i
>= 0; i
--) {
1329 int ptshift
= i
* vm
.idxbits
;
1330 reg_t idx
= (vaddr
>> (PGSHIFT
+ ptshift
)) & ((1 << vm
.idxbits
) - 1);
1332 reg_t pte_addr
= base
+ idx
* vm
.ptesize
;
1333 auto it
= pte_cache
.find(pte_addr
);
1334 if (it
== pte_cache
.end()) {
1335 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1336 " without first collecting the relevant PTEs.\n", vaddr
);
1337 die("gdbserver_t::translate()");
1340 reg_t pte
= pte_cache
[pte_addr
];
1341 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
1343 if (PTE_TABLE(pte
)) { // next level of page table
1344 base
= ppn
<< PGSHIFT
;
1346 // We've collected all the data required for the translation.
1347 reg_t vpn
= vaddr
>> PGSHIFT
;
1348 reg_t paddr
= (ppn
| (vpn
& ((reg_t(1) << ptshift
) - 1))) << PGSHIFT
;
1349 paddr
+= vaddr
& (PGSIZE
-1);
1350 D(fprintf(stderr
, "gdbserver translate 0x%" PRIx64
" -> 0x%" PRIx64
"\n", vaddr
, paddr
));
1355 fprintf(stderr
, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1356 " but the relevant PTEs are invalid.\n", vaddr
);
1357 // TODO: Is it better to throw an exception here?
1361 unsigned int gdbserver_t::privilege_mode()
1363 unsigned int mode
= get_field(dcsr
, DCSR_PRV
);
1364 if (get_field(mstatus
, MSTATUS_MPRV
))
1365 mode
= get_field(mstatus
, MSTATUS_MPP
);
1369 void gdbserver_t::dr_write32(unsigned int index
, uint32_t value
)
1371 sim
->debug_module
.ram_write32(index
, value
);
1374 void gdbserver_t::dr_write64(unsigned int index
, uint64_t value
)
1376 dr_write32(index
, value
);
1377 dr_write32(index
+1, value
>> 32);
1380 void gdbserver_t::dr_write(enum slot slot
, uint64_t value
)
1384 dr_write32(slot_offset32
[slot
], value
);
1387 dr_write64(slot_offset64
[slot
], value
);
1395 void gdbserver_t::dr_write_jump(unsigned int index
)
1397 dr_write32(index
, jal(0,
1398 (uint32_t) (DEBUG_ROM_RESUME
- (DEBUG_RAM_START
+ 4*index
))));
1401 void gdbserver_t::dr_write_store(unsigned int index
, unsigned int reg
, enum slot slot
)
1403 assert(slot
!= SLOT_INST0
|| index
> 2);
1404 assert(slot
!= SLOT_DATA0
|| index
< 4 || index
> 6);
1405 assert(slot
!= SLOT_DATA1
|| index
< 5 || index
> 10);
1406 assert(slot
!= SLOT_DATA_LAST
|| index
< 6 || index
> 14);
1409 return dr_write32(index
,
1410 sw(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset32
[slot
]));
1412 return dr_write32(index
,
1413 sd(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset64
[slot
]));
1415 return dr_write32(index
,
1416 sq(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset128
[slot
]));
1418 fprintf(stderr
, "xlen is %d!\n", xlen
);
1423 void gdbserver_t::dr_write_load(unsigned int index
, unsigned int reg
, enum slot slot
)
1427 return dr_write32(index
,
1428 lw(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset32
[slot
]));
1430 return dr_write32(index
,
1431 ld(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset64
[slot
]));
1433 return dr_write32(index
,
1434 lq(reg
, 0, (uint16_t) DEBUG_RAM_START
+ 4 * slot_offset128
[slot
]));
1436 fprintf(stderr
, "xlen is %d!\n", xlen
);
1441 uint32_t gdbserver_t::dr_read32(unsigned int index
)
1443 uint32_t value
= sim
->debug_module
.ram_read32(index
);
1444 D(fprintf(stderr
, "read32(%d) -> 0x%x\n", index
, value
));
1448 uint64_t gdbserver_t::dr_read64(unsigned int index
)
1450 return ((uint64_t) dr_read32(index
+1) << 32) | dr_read32(index
);
1453 uint64_t gdbserver_t::dr_read(enum slot slot
)
1457 return dr_read32(slot_offset32
[slot
]);
1459 return dr_read64(slot_offset64
[slot
]);
1467 void gdbserver_t::add_operation(operation_t
* operation
)
1469 operation_queue
.push(operation
);
1472 void gdbserver_t::accept()
1474 client_fd
= ::accept(socket_fd
, NULL
, NULL
);
1475 if (client_fd
== -1) {
1476 if (errno
== EAGAIN
) {
1477 // No client waiting to connect right now.
1479 fprintf(stderr
, "failed to accept on socket: %s (%d)\n", strerror(errno
),
1484 fcntl(client_fd
, F_SETFL
, O_NONBLOCK
);
1487 extended_mode
= false;
1489 // gdb wants the core to be halted when it attaches.
1490 add_operation(new halt_op_t(*this));
1494 void gdbserver_t::read()
1496 // Reading from a non-blocking socket still blocks if there is no data
1499 size_t count
= recv_buf
.contiguous_empty_size();
1500 ssize_t bytes
= ::read(client_fd
, recv_buf
.contiguous_empty(), count
);
1502 if (errno
== EAGAIN
) {
1503 // We'll try again the next call.
1505 fprintf(stderr
, "failed to read on socket: %s (%d)\n", strerror(errno
), errno
);
1508 } else if (bytes
== 0) {
1509 // The remote disconnected.
1511 processor_t
*p
= sim
->get_core(0);
1512 // TODO p->set_halted(false, HR_NONE);
1516 recv_buf
.data_added(bytes
);
1520 void gdbserver_t::write()
1522 if (send_buf
.empty())
1525 while (!send_buf
.empty()) {
1526 unsigned int count
= send_buf
.contiguous_data_size();
1528 ssize_t bytes
= ::write(client_fd
, send_buf
.contiguous_data(), count
);
1530 fprintf(stderr
, "failed to write to socket: %s (%d)\n", strerror(errno
), errno
);
1532 } else if (bytes
== 0) {
1533 // Client can't take any more data right now.
1536 D(fprintf(stderr
, "wrote %zd bytes: ", bytes
));
1537 for (int i
= 0; i
< bytes
; i
++) {
1538 D(fprintf(stderr
, "%c", send_buf
[i
]));
1540 D(fprintf(stderr
, "\n"));
1541 send_buf
.consume(bytes
);
1546 void print_packet(const std::vector
<uint8_t> &packet
)
1548 for (uint8_t c
: packet
) {
1549 if (c
>= ' ' and c
<= '~')
1550 fprintf(stderr
, "%c", c
);
1552 fprintf(stderr
, "\\x%02x", c
);
1554 fprintf(stderr
, "\n");
1557 uint8_t compute_checksum(const std::vector
<uint8_t> &packet
)
1559 uint8_t checksum
= 0;
1560 for (auto i
= packet
.begin() + 1; i
!= packet
.end() - 3; i
++ ) {
1566 uint8_t character_hex_value(uint8_t character
)
1568 if (character
>= '0' && character
<= '9')
1569 return character
- '0';
1570 if (character
>= 'a' && character
<= 'f')
1571 return 10 + character
- 'a';
1572 if (character
>= 'A' && character
<= 'F')
1573 return 10 + character
- 'A';
1577 uint8_t extract_checksum(const std::vector
<uint8_t> &packet
)
1579 return character_hex_value(*(packet
.end() - 1)) +
1580 16 * character_hex_value(*(packet
.end() - 2));
1583 void gdbserver_t::process_requests()
1585 // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1587 while (!recv_buf
.empty()) {
1588 std::vector
<uint8_t> packet
;
1589 for (unsigned int i
= 0; i
< recv_buf
.size(); i
++) {
1590 uint8_t b
= recv_buf
[i
];
1592 if (packet
.empty() && expect_ack
&& b
== '+') {
1593 recv_buf
.consume(1);
1597 if (packet
.empty() && b
== 3) {
1598 D(fprintf(stderr
, "Received interrupt\n"));
1599 recv_buf
.consume(1);
1605 // Start of new packet.
1606 if (!packet
.empty()) {
1607 fprintf(stderr
, "Received malformed %zd-byte packet from debug client: ",
1609 print_packet(packet
);
1610 recv_buf
.consume(i
);
1615 packet
.push_back(b
);
1617 // Packets consist of $<packet-data>#<checksum>
1618 // where <checksum> is
1619 if (packet
.size() >= 4 &&
1620 packet
[packet
.size()-3] == '#') {
1621 handle_packet(packet
);
1622 recv_buf
.consume(i
+1);
1626 // There's a partial packet in the buffer. Wait until we get more data to
1628 if (packet
.size()) {
1633 if (recv_buf
.full()) {
1635 "Receive buffer is full, but no complete packet was found!\n");
1636 for (unsigned line
= 0; line
< 8; line
++) {
1637 for (unsigned i
= 0; i
< 16; i
++) {
1638 fprintf(stderr
, "%02x ", recv_buf
.entry(line
* 16 + i
));
1640 for (unsigned i
= 0; i
< 16; i
++) {
1641 uint8_t e
= recv_buf
.entry(line
* 16 + i
);
1642 if (e
>= ' ' && e
<= '~')
1643 fprintf(stderr
, "%c", e
);
1645 fprintf(stderr
, ".");
1647 fprintf(stderr
, "\n");
1649 assert(!recv_buf
.full());
1653 void gdbserver_t::handle_halt_reason(const std::vector
<uint8_t> &packet
)
1658 void gdbserver_t::handle_general_registers_read(const std::vector
<uint8_t> &packet
)
1660 add_operation(new general_registers_read_op_t(*this));
1663 void gdbserver_t::set_interrupt(uint32_t hartid
) {
1664 sim
->debug_module
.set_interrupt(hartid
);
1667 // First byte is the most-significant one.
1668 // Eg. "08675309" becomes 0x08675309.
1669 uint64_t consume_hex_number(std::vector
<uint8_t>::const_iterator
&iter
,
1670 std::vector
<uint8_t>::const_iterator end
)
1674 while (iter
!= end
) {
1676 uint64_t c_value
= character_hex_value(c
);
1686 // First byte is the least-significant one.
1687 // Eg. "08675309" becomes 0x09536708
1688 uint64_t gdbserver_t::consume_hex_number_le(
1689 std::vector
<uint8_t>::const_iterator
&iter
,
1690 std::vector
<uint8_t>::const_iterator end
)
1693 unsigned int shift
= 4;
1695 while (iter
!= end
) {
1697 uint64_t c_value
= character_hex_value(c
);
1701 value
|= c_value
<< shift
;
1702 if ((shift
% 8) == 0)
1707 if (shift
> (xlen
+4)) {
1709 "gdb sent too many data bytes. That means it thinks XLEN is greater "
1710 "than %d.\nTo fix that, tell gdb: set arch riscv:rv%d\n",
1716 void consume_string(std::string
&str
, std::vector
<uint8_t>::const_iterator
&iter
,
1717 std::vector
<uint8_t>::const_iterator end
, uint8_t separator
)
1719 while (iter
!= end
&& *iter
!= separator
) {
1720 str
.append(1, (char) *iter
);
1725 void gdbserver_t::handle_register_read(const std::vector
<uint8_t> &packet
)
1729 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1730 unsigned int n
= consume_hex_number(iter
, packet
.end());
1732 return send_packet("E01");
1734 add_operation(new register_read_op_t(*this, n
));
1737 void gdbserver_t::handle_register_write(const std::vector
<uint8_t> &packet
)
1741 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1742 unsigned int n
= consume_hex_number(iter
, packet
.end());
1744 return send_packet("E05");
1747 reg_t value
= consume_hex_number_le(iter
, packet
.end());
1749 return send_packet("E06");
1751 processor_t
*p
= sim
->get_core(0);
1753 add_operation(new register_write_op_t(*this, n
, value
));
1756 void gdbserver_t::handle_memory_read(const std::vector
<uint8_t> &packet
)
1759 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1760 reg_t address
= consume_hex_number(iter
, packet
.end());
1762 return send_packet("E10");
1764 reg_t length
= consume_hex_number(iter
, packet
.end());
1766 return send_packet("E11");
1768 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1769 add_operation(new memory_read_op_t(*this, address
, length
));
1772 void gdbserver_t::handle_memory_binary_write(const std::vector
<uint8_t> &packet
)
1774 // X addr,length:XX...
1775 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1776 reg_t address
= consume_hex_number(iter
, packet
.end());
1778 return send_packet("E20");
1780 reg_t length
= consume_hex_number(iter
, packet
.end());
1782 return send_packet("E21");
1786 return send_packet("OK");
1789 unsigned char *data
= new unsigned char[length
];
1790 for (unsigned int i
= 0; i
< length
; i
++) {
1791 if (iter
== packet
.end()) {
1792 return send_packet("E22");
1797 // The binary data representation uses 7d (ascii ‘}’) as an escape
1798 // character. Any escaped byte is transmitted as the escape character
1799 // followed by the original character XORed with 0x20. For example, the
1800 // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1801 // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1803 if (iter
== packet
.end()) {
1804 return send_packet("E23");
1812 return send_packet("E4b"); // EOVERFLOW
1814 add_operation(new collect_translation_info_op_t(*this, address
, length
));
1815 add_operation(new memory_write_op_t(*this, address
, length
, data
));
1818 void gdbserver_t::handle_continue(const std::vector
<uint8_t> &packet
)
1821 processor_t
*p
= sim
->get_core(0);
1822 if (packet
[2] != '#') {
1823 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1824 dpc
= consume_hex_number(iter
, packet
.end());
1826 return send_packet("E30");
1829 add_operation(new maybe_restore_tselect_op_t(*this));
1830 add_operation(new maybe_restore_mstatus_op_t(*this));
1831 add_operation(new continue_op_t(*this, false));
1834 void gdbserver_t::handle_step(const std::vector
<uint8_t> &packet
)
1837 if (packet
[2] != '#') {
1838 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1840 //p->state.pc = consume_hex_number(iter, packet.end());
1842 return send_packet("E40");
1845 add_operation(new maybe_restore_tselect_op_t(*this));
1846 add_operation(new continue_op_t(*this, true));
1849 void gdbserver_t::handle_kill(const std::vector
<uint8_t> &packet
)
1852 // The exact effect of this packet is not specified.
1853 // Looks like OpenOCD disconnects?
1857 void gdbserver_t::handle_extended(const std::vector
<uint8_t> &packet
)
1859 // Enable extended mode. In extended mode, the remote server is made
1860 // persistent. The ‘R’ packet is used to restart the program being debugged.
1862 extended_mode
= true;
1865 void gdbserver_t::software_breakpoint_insert(reg_t vaddr
, unsigned int size
)
1867 fence_i_required
= true;
1868 add_operation(new collect_translation_info_op_t(*this, vaddr
, size
));
1869 unsigned char* inst
= new unsigned char[4];
1871 inst
[0] = MATCH_C_EBREAK
& 0xff;
1872 inst
[1] = (MATCH_C_EBREAK
>> 8) & 0xff;
1874 inst
[0] = MATCH_EBREAK
& 0xff;
1875 inst
[1] = (MATCH_EBREAK
>> 8) & 0xff;
1876 inst
[2] = (MATCH_EBREAK
>> 16) & 0xff;
1877 inst
[3] = (MATCH_EBREAK
>> 24) & 0xff;
1880 software_breakpoint_t bp
= {
1884 software_breakpoints
[vaddr
] = bp
;
1885 add_operation(new memory_read_op_t(*this, bp
.vaddr
, bp
.size
,
1886 software_breakpoints
[bp
.vaddr
].instruction
));
1887 add_operation(new memory_write_op_t(*this, bp
.vaddr
, bp
.size
, inst
));
1890 void gdbserver_t::software_breakpoint_remove(reg_t vaddr
, unsigned int size
)
1892 fence_i_required
= true;
1893 add_operation(new collect_translation_info_op_t(*this, vaddr
, size
));
1895 software_breakpoint_t found_bp
= software_breakpoints
[vaddr
];
1896 unsigned char* instruction
= new unsigned char[4];
1897 memcpy(instruction
, found_bp
.instruction
, 4);
1898 add_operation(new memory_write_op_t(*this, found_bp
.vaddr
,
1899 found_bp
.size
, instruction
));
1900 software_breakpoints
.erase(vaddr
);
1903 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t
&bp
)
1905 add_operation(new maybe_save_tselect_op_t(*this));
1906 add_operation(new hardware_breakpoint_insert_op_t(*this, bp
));
1909 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t
&bp
)
1911 add_operation(new maybe_save_tselect_op_t(*this));
1912 hardware_breakpoint_t found
= *hardware_breakpoints
.find(bp
);
1913 add_operation(new hardware_breakpoint_remove_op_t(*this, found
));
1916 void gdbserver_t::handle_breakpoint(const std::vector
<uint8_t> &packet
)
1918 // insert: Z type,addr,length
1919 // remove: z type,addr,length
1921 // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1922 // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1923 // length is in bytes. For a software breakpoint, length specifies the size
1924 // of the instruction to be patched. For hardware breakpoints and watchpoints
1925 // length specifies the memory region to be monitored. To avoid potential
1926 // problems with duplicate packets, the operations should be implemented in
1927 // an idempotent way.
1929 bool insert
= (packet
[1] == 'Z');
1930 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1931 gdb_breakpoint_type_t type
= static_cast<gdb_breakpoint_type_t
>(
1932 consume_hex_number(iter
, packet
.end()));
1934 return send_packet("E50");
1936 reg_t address
= consume_hex_number(iter
, packet
.end());
1938 return send_packet("E51");
1940 unsigned int size
= consume_hex_number(iter
, packet
.end());
1941 // There may be more options after a ; here, but we don't support that.
1943 return send_packet("E52");
1947 if (size
!= 2 && size
!= 4) {
1948 return send_packet("E53");
1951 software_breakpoint_insert(address
, size
);
1953 software_breakpoint_remove(address
, size
);
1962 hardware_breakpoint_t bp
= {
1966 bp
.load
= (type
== GB_READ
|| type
== GB_ACCESS
);
1967 bp
.store
= (type
== GB_WRITE
|| type
== GB_ACCESS
);
1968 bp
.execute
= (type
== GB_HARDWARE
|| type
== GB_ACCESS
);
1970 hardware_breakpoint_insert(bp
);
1971 // Insert might fail if there's no space, so the insert operation will
1972 // send its own OK (or not).
1975 hardware_breakpoint_remove(bp
);
1981 return send_packet("E56");
1984 return send_packet("OK");
1987 void gdbserver_t::handle_query(const std::vector
<uint8_t> &packet
)
1990 std::vector
<uint8_t>::const_iterator iter
= packet
.begin() + 2;
1992 consume_string(name
, iter
, packet
.end(), ':');
1993 if (iter
!= packet
.end())
1995 if (name
== "Supported") {
1997 while (iter
!= packet
.end()) {
1998 std::string feature
;
1999 consume_string(feature
, iter
, packet
.end(), ';');
2000 if (iter
!= packet
.end())
2002 if (feature
== "swbreak+") {
2006 send("PacketSize=131072;");
2007 return end_packet();
2010 D(fprintf(stderr
, "Unsupported query %s\n", name
.c_str()));
2011 return send_packet("");
2014 void gdbserver_t::handle_packet(const std::vector
<uint8_t> &packet
)
2016 if (compute_checksum(packet
) != extract_checksum(packet
)) {
2017 fprintf(stderr
, "Received %zd-byte packet with invalid checksum\n", packet
.size());
2018 fprintf(stderr
, "Computed checksum: %x\n", compute_checksum(packet
));
2019 print_packet(packet
);
2024 D(fprintf(stderr
, "Received %zd-byte packet from debug client: ", packet
.size()));
2025 D(print_packet(packet
));
2028 switch (packet
[1]) {
2030 return handle_extended(packet
);
2032 return handle_halt_reason(packet
);
2034 return handle_general_registers_read(packet
);
2036 // return handle_kill(packet);
2038 return handle_memory_read(packet
);
2040 // return handle_memory_write(packet);
2042 return handle_memory_binary_write(packet
);
2044 return handle_register_read(packet
);
2046 return handle_register_write(packet
);
2048 return handle_continue(packet
);
2050 return handle_step(packet
);
2053 return handle_breakpoint(packet
);
2056 return handle_query(packet
);
2060 D(fprintf(stderr
, "** Unsupported packet: "));
2061 D(print_packet(packet
));
2065 void gdbserver_t::handle_interrupt()
2067 processor_t
*p
= sim
->get_core(0);
2068 add_operation(new halt_op_t(*this, true));
2071 void gdbserver_t::handle()
2073 if (client_fd
> 0) {
2074 processor_t
*p
= sim
->get_core(0);
2076 bool interrupt
= sim
->debug_module
.get_interrupt(0);
2078 if (!interrupt
&& !operation_queue
.empty()) {
2079 operation_t
*operation
= operation_queue
.front();
2080 if (operation
->step()) {
2081 operation_queue
.pop();
2086 bool halt_notification
= sim
->debug_module
.get_halt_notification(0);
2087 if (halt_notification
) {
2088 sim
->debug_module
.clear_halt_notification(0);
2089 add_operation(new halt_op_t(*this, true));
2099 if (operation_queue
.empty()) {
2100 this->process_requests();
2104 void gdbserver_t::send(const char* msg
)
2106 unsigned int length
= strlen(msg
);
2107 for (const char *c
= msg
; *c
; c
++)
2108 running_checksum
+= *c
;
2109 send_buf
.append((const uint8_t *) msg
, length
);
2112 void gdbserver_t::send(uint64_t value
)
2115 for (unsigned int i
= 0; i
< 8; i
++) {
2116 sprintf(buffer
, "%02x", (int) (value
& 0xff));
2122 void gdbserver_t::send(uint32_t value
)
2125 for (unsigned int i
= 0; i
< 4; i
++) {
2126 sprintf(buffer
, "%02x", (int) (value
& 0xff));
2132 void gdbserver_t::send(uint8_t value
)
2135 sprintf(buffer
, "%02x", (int) value
);
2139 void gdbserver_t::send_packet(const char* data
)
2147 void gdbserver_t::start_packet()
2150 running_checksum
= 0;
2153 void gdbserver_t::end_packet(const char* data
)
2159 char checksum_string
[4];
2160 sprintf(checksum_string
, "#%02x", running_checksum
);
2161 send(checksum_string
);