projects
/
riscv-isa-sim.git
/ blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
history
|
raw
|
HEAD
sim: define emulated CPU clock rate to be 1GHz
[riscv-isa-sim.git]
/
riscv
/
insns
/
amoor_w.h
1
require_extension
(
'A'
);
2
WRITE_RD
(
sext32
(
MMU
.
amo_uint32
(
RS1
, [&](
uint32_t
lhs
) {
return
lhs
|
RS2
; })));