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f2fc2991d32a0fe5925cf048c8a6bf9fb0892605
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_lw.h
1
require_extension
(
'C'
);
2
WRITE_RVC_RDS
(
MMU
.
load_int32
(
RVC_RS1S
+
insn
.
rvc_lw_imm
()));