96d9e10ecacbff95bd4e6ae06d35bf0179b44a15
[riscv-isa-sim.git] / riscv / insns / div.h
1 if(RS2 == 0)
2 RD = UINT64_MAX;
3 else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
4 RD = RS1;
5 else
6 RD = sext_xprlen(sreg_t(RS1) / sreg_t(RS2));