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HEAD
Use WRITE_RD/WRITE_FRD macros to write registers
[riscv-isa-sim.git]
/
riscv
/
insns
/
div.h
1
sreg_t lhs
=
sext_xprlen
(
RS1
);
2
sreg_t rhs
=
sext_xprlen
(
RS2
);
3
if
(
rhs
==
0
)
4
WRITE_RD
(
UINT64_MAX
);
5
else if
(
lhs
==
INT64_MIN
&&
rhs
== -
1
)
6
WRITE_RD
(
lhs
);
7
else
8
WRITE_RD
(
sext_xprlen
(
lhs
/
rhs
));