cd968bdeb41c4b60d947880d8aedbb7066d5e2e0
[riscv-isa-sim.git] / riscv / insns / eret.h
1 require_supervisor;
2 if(sr & SR_ET)
3 throw trap_illegal_instruction;
4 set_pcr(PCR_SR, ((sr & SR_PS) ? sr : (sr & ~SR_S)) | SR_ET);
5 set_pc(epc);