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088480cba7e4f18c96b5998a98284084df67cf25
[riscv-isa-sim.git]
/
riscv
/
insns
/
mfcr.h
1
reg_t val
;
2
3
switch
(
insn
.
rtype
.
rb
)
4
{
5
case
0
:
6
val
=
fsr
;
7
break
;
8
9
case
1
:
10
val
=
32
;
// synci_step
11
break
;
12
13
case
29
:
14
val
=
tid
;
15
break
;
16
17
default
:
18
val
= -
1
;
19
}
20
21
RC
=
gprlen
==
64
?
val
:
sext32
(
val
);