riscv/insns/mtpcr.h

   1 require_supervisor;
   2
   3 switch(insn.rtype.rb)
   4 {
   5   case 0:
   6     set_sr(RA);
   7     break;
   8   case 1:
   9     epc = RA;
  10     break;
  11   case 3:
  12     ebase = RA & ~0xFFF;
  13     break;
  14   case 4:
  15     count = RA;
  16     break;
  17   case 5:
  18     interrupts_pending &= ~(1 << TIMER_IRQ);
  19     compare = RA;
  20     break;
  21
  22   case 16:
  23     tohost = RA;
  24     sim->set_tohost(RA);
  25     break;
  26
  27   case 24:
  28     pcr_k0 = RA;
  29     break;
  30   case 25:
  31     pcr_k1 = RA;
  32     break;
  33 }