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ceefccd91bad7b6a47c3a2a85337d4962fa36185
[riscv-isa-sim.git]
/
riscv
/
insns
/
mulh.h
1
if
(
xpr64
)
2
{
3
int64_t
a
=
RS1
;
4
int64_t
b
=
RS2
;
5
RD
= (
int128_t
(
a
) *
int128_t
(
b
)) >>
64
;
6
}
7
else
8
RD
=
sext32
((
sreg_t
(
RS1
) *
sreg_t
(
RS2
)) >>
32
);