ae28fa567ebe437f4fdbe1ad89d80e0f2f98df04
[riscv-isa-sim.git] / riscv / insns / remuw.h
1 require_xpr64;
2 if(RS2 == 0)
3 RD = RS1;
4 else
5 RD = sext32(RS1 % RS2);