7fdbdf33c8cbcf579c5544aca3b48ed5a5cfd7ce
[riscv-isa-sim.git] / riscv / insns / srai.h
1 if(xpr64)
2 WRITE_RD(sreg_t(RS1) >> SHAMT);
3 else
4 {
5 if(SHAMT & 0x20)
6 throw trap_illegal_instruction();
7 WRITE_RD(sext32(int32_t(RS1) >> SHAMT));
8 }