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4c5673007d1dcd9e4d169136c7df2ed8a5041908
[riscv-isa-sim.git]
/
riscv
/
insns
/
sraiw.h
1
require_xpr64
;
2
RD
=
sext32
(
int32_t
(
RS1
) >>
SHAMTW
);