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103f03a3184b4866864af29ffe3f89557831f3c0
[riscv-isa-sim.git]
/
riscv
/
insns
/
sraw.h
1
require_xpr64
;
2
RD
=
sext32
(
sreg_t
(
RS1
) >> (
RS2
&
0x1F
));