5fcc30305dd3082e6a6b899e6ea2f0bf183b876d
5 #include "debug_module.h"
19 #define DTMCONTROL_VERSION 0xf
20 #define DTMCONTROL_ABITS (0x3f << 4)
21 #define DTMCONTROL_DBUSSTAT (3<<10)
22 #define DTMCONTROL_IDLE (7<<12)
23 #define DTMCONTROL_DBUSRESET (1<<16)
26 #define DBUS_DATA (0xffffffffL<<2)
27 #define DBUS_ADDRESS ((1L<<(abits+34)) - (1L<<34))
29 #define DBUS_OP_STATUS_SUCCESS 0
30 #define DBUS_OP_STATUS_RESERVED 1
31 #define DBUS_OP_STATUS_FAILED 2
32 #define DBUS_OP_STATUS_BUSY 3
35 #define DBUS_OP_READ 1
36 #define DBUS_OP_READ_WRITE 2
37 #define DBUS_OP_RESERVED 3
39 jtag_dtm_t::jtag_dtm_t(debug_module_t
*dm
) :
41 dtmcontrol((abits
<< 4) | 1),
43 state(TEST_LOGIC_RESET
)
47 void jtag_dtm_t::reset() {
48 state
= TEST_LOGIC_RESET
;
51 void jtag_dtm_t::set_pins(bool tck
, bool tms
, bool tdi
) {
52 const jtag_state_t next
[16][2] = {
53 /* TEST_LOGIC_RESET */ { RUN_TEST_IDLE
, TEST_LOGIC_RESET
},
54 /* RUN_TEST_IDLE */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
55 /* SELECT_DR_SCAN */ { CAPTURE_DR
, SELECT_IR_SCAN
},
56 /* CAPTURE_DR */ { SHIFT_DR
, EXIT1_DR
},
57 /* SHIFT_DR */ { SHIFT_DR
, EXIT1_DR
},
58 /* EXIT1_DR */ { PAUSE_DR
, UPDATE_DR
},
59 /* PAUSE_DR */ { PAUSE_DR
, EXIT2_DR
},
60 /* EXIT2_DR */ { SHIFT_DR
, UPDATE_DR
},
61 /* UPDATE_DR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
},
62 /* SELECT_IR_SCAN */ { CAPTURE_IR
, TEST_LOGIC_RESET
},
63 /* CAPTURE_IR */ { SHIFT_IR
, EXIT1_IR
},
64 /* SHIFT_IR */ { SHIFT_IR
, EXIT1_IR
},
65 /* EXIT1_IR */ { PAUSE_IR
, UPDATE_IR
},
66 /* PAUSE_IR */ { PAUSE_IR
, EXIT2_IR
},
67 /* EXIT2_IR */ { SHIFT_IR
, UPDATE_IR
},
68 /* UPDATE_IR */ { RUN_TEST_IDLE
, SELECT_DR_SCAN
}
72 // Positive clock edge.
77 dr
|= (uint64_t) _tdi
<< (dr_length
-1);
81 ir
|= _tdi
<< (ir_length
-1);
86 state
= next
[state
][_tms
];
88 case TEST_LOGIC_RESET
:
112 D(fprintf(stderr
, "state=%2d, tdi=%d, tdo=%d, tms=%d, tck=%d, ir=0x%02x, dr=0x%lx\n",
113 state
, _tdi
, _tdo
, _tms
, _tck
, ir
, dr
));
120 void jtag_dtm_t::capture_dr()
133 dr_length
= abits
+ 34;
136 D(fprintf(stderr
, "Unsupported IR: 0x%x\n", ir
));
139 D(fprintf(stderr
, "Capture DR; IR=0x%x, DR=0x%lx (%d bits)\n",
143 void jtag_dtm_t::update_dr()
145 D(fprintf(stderr
, "Update DR; IR=0x%x, DR=0x%lx (%d bits)\n",
150 unsigned op
= get_field(dr
, DBUS_OP
);
151 uint32_t data
= get_field(dr
, DBUS_DATA
);
152 unsigned address
= get_field(dr
, DBUS_ADDRESS
);
156 if (op
== DBUS_OP_READ
|| op
== DBUS_OP_READ_WRITE
) {
157 dbus
= set_field(dbus
, DBUS_DATA
, dm
->dmi_read(address
));
159 if (op
== DBUS_OP_READ_WRITE
) {
160 dm
->dmi_write(address
, data
);
163 dbus
= set_field(dbus
, DBUS_OP
, DBUS_OP_STATUS_SUCCESS
);