0b60713fd376fb2c999334b6386c05b80eea4bca
1 // See LICENSE for license details.
7 mmu_t::mmu_t(sim_t
* sim
, processor_t
* proc
)
8 : sim(sim
), proc(proc
),
9 check_triggers_fetch(false),
10 check_triggers_load(false),
11 check_triggers_store(false),
21 void mmu_t::flush_icache()
23 for (size_t i
= 0; i
< ICACHE_ENTRIES
; i
++)
27 void mmu_t::flush_tlb()
29 memset(tlb_insn_tag
, -1, sizeof(tlb_insn_tag
));
30 memset(tlb_load_tag
, -1, sizeof(tlb_load_tag
));
31 memset(tlb_store_tag
, -1, sizeof(tlb_store_tag
));
36 reg_t
mmu_t::translate(reg_t addr
, access_type type
)
41 reg_t mode
= proc
->state
.prv
;
43 if (!proc
->state
.dcsr
.cause
&& get_field(proc
->state
.mstatus
, MSTATUS_MPRV
))
44 mode
= get_field(proc
->state
.mstatus
, MSTATUS_MPP
);
46 if (get_field(proc
->state
.mstatus
, MSTATUS_VM
) == VM_MBARE
)
50 reg_t msb_mask
= (reg_t(2) << (proc
->xlen
-1))-1; // zero-extend from xlen
51 return addr
& msb_mask
;
53 return walk(addr
, type
, mode
) | (addr
& (PGSIZE
-1));
56 const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr
)
58 reg_t paddr
= translate(vaddr
, FETCH
);
60 // mmu_t::walk() returns -1 if it can't find a match. Of course -1 could also
61 // be a valid address.
62 if (paddr
== ~(reg_t
) 0 && vaddr
!= ~(reg_t
) 0) {
63 throw trap_instruction_access_fault(vaddr
);
66 if (sim
->addr_is_mem(paddr
)) {
67 refill_tlb(vaddr
, paddr
, FETCH
);
68 return (const uint16_t*)sim
->addr_to_mem(paddr
);
70 if (!sim
->mmio_load(paddr
, sizeof fetch_temp
, (uint8_t*)&fetch_temp
))
71 throw trap_instruction_access_fault(vaddr
);
76 void mmu_t::load_slow_path(reg_t addr
, reg_t len
, uint8_t* bytes
)
78 reg_t paddr
= translate(addr
, LOAD
);
79 if (sim
->addr_is_mem(paddr
)) {
80 memcpy(bytes
, sim
->addr_to_mem(paddr
), len
);
81 if (tracer
.interested_in_range(paddr
, paddr
+ PGSIZE
, LOAD
))
82 tracer
.trace(paddr
, len
, LOAD
);
84 refill_tlb(addr
, paddr
, LOAD
);
85 } else if (!sim
->mmio_load(paddr
, len
, bytes
)) {
86 throw trap_load_access_fault(addr
);
90 void mmu_t::store_slow_path(reg_t addr
, reg_t len
, const uint8_t* bytes
)
92 reg_t paddr
= translate(addr
, STORE
);
93 if (sim
->addr_is_mem(paddr
)) {
94 memcpy(sim
->addr_to_mem(paddr
), bytes
, len
);
95 if (tracer
.interested_in_range(paddr
, paddr
+ PGSIZE
, STORE
))
96 tracer
.trace(paddr
, len
, STORE
);
98 refill_tlb(addr
, paddr
, STORE
);
99 } else if (!sim
->mmio_store(paddr
, len
, bytes
)) {
100 throw trap_store_access_fault(addr
);
104 void mmu_t::refill_tlb(reg_t vaddr
, reg_t paddr
, access_type type
)
106 reg_t idx
= (vaddr
>> PGSHIFT
) % TLB_ENTRIES
;
107 reg_t expected_tag
= vaddr
>> PGSHIFT
;
109 if ((tlb_load_tag
[idx
] & ~TLB_CHECK_TRIGGERS
) != expected_tag
)
110 tlb_load_tag
[idx
] = -1;
111 if ((tlb_store_tag
[idx
] & ~TLB_CHECK_TRIGGERS
) != expected_tag
)
112 tlb_store_tag
[idx
] = -1;
113 if ((tlb_insn_tag
[idx
] & ~TLB_CHECK_TRIGGERS
) != expected_tag
)
114 tlb_insn_tag
[idx
] = -1;
116 if ((check_triggers_fetch
&& type
== FETCH
) ||
117 (check_triggers_load
&& type
== LOAD
) ||
118 (check_triggers_store
&& type
== STORE
))
119 expected_tag
|= TLB_CHECK_TRIGGERS
;
121 if (type
== FETCH
) tlb_insn_tag
[idx
] = expected_tag
;
122 else if (type
== STORE
) tlb_store_tag
[idx
] = expected_tag
;
123 else tlb_load_tag
[idx
] = expected_tag
;
125 tlb_data
[idx
] = sim
->addr_to_mem(paddr
) - vaddr
;
128 reg_t
mmu_t::walk(reg_t addr
, access_type type
, reg_t mode
)
130 int levels
, ptidxbits
, ptesize
;
131 switch (get_field(proc
->get_state()->mstatus
, MSTATUS_VM
))
133 case VM_SV32
: levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
134 case VM_SV39
: levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
135 case VM_SV48
: levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
139 bool supervisor
= mode
== PRV_S
;
140 bool pum
= get_field(proc
->state
.mstatus
, MSTATUS_PUM
);
141 bool mxr
= get_field(proc
->state
.mstatus
, MSTATUS_MXR
);
143 // verify bits xlen-1:va_bits-1 are all equal
144 int va_bits
= PGSHIFT
+ levels
* ptidxbits
;
145 reg_t mask
= (reg_t(1) << (proc
->xlen
- (va_bits
-1))) - 1;
146 reg_t masked_msbs
= (addr
>> (va_bits
-1)) & mask
;
147 if (masked_msbs
!= 0 && masked_msbs
!= mask
)
150 reg_t base
= proc
->get_state()->sptbr
<< PGSHIFT
;
151 int ptshift
= (levels
- 1) * ptidxbits
;
152 for (int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
153 reg_t idx
= (addr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
155 // check that physical address of PTE is legal
156 reg_t pte_addr
= base
+ idx
* ptesize
;
157 if (!sim
->addr_is_mem(pte_addr
))
160 void* ppte
= sim
->addr_to_mem(pte_addr
);
161 reg_t pte
= ptesize
== 4 ? *(uint32_t*)ppte
: *(uint64_t*)ppte
;
162 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
164 if (PTE_TABLE(pte
)) { // next level of page table
165 base
= ppn
<< PGSHIFT
;
166 } else if ((pte
& PTE_U
) ? supervisor
&& pum
: !supervisor
) {
168 } else if (!(pte
& PTE_V
) || (!(pte
& PTE_R
) && (pte
& PTE_W
))) {
170 } else if (type
== FETCH
? !(pte
& PTE_X
) :
171 type
== LOAD
? !(pte
& PTE_R
) && !(mxr
&& (pte
& PTE_X
)) :
172 !((pte
& PTE_R
) && (pte
& PTE_W
))) {
175 // set accessed and possibly dirty bits.
176 *(uint32_t*)ppte
|= PTE_A
| ((type
== STORE
) * PTE_D
);
177 // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
178 reg_t vpn
= addr
>> PGSHIFT
;
179 reg_t value
= (ppn
| (vpn
& ((reg_t(1) << ptshift
) - 1))) << PGSHIFT
;
187 void mmu_t::register_memtracer(memtracer_t
* t
)