1 // See LICENSE for license details.
7 mmu_t::mmu_t(char* _mem
, size_t _memsz
)
8 : mem(_mem
), memsz(_memsz
), proc(NULL
)
17 void mmu_t::flush_icache()
19 for (size_t i
= 0; i
< ICACHE_ENTRIES
; i
++)
23 void mmu_t::flush_tlb()
25 memset(tlb_insn_tag
, -1, sizeof(tlb_insn_tag
));
26 memset(tlb_load_tag
, -1, sizeof(tlb_load_tag
));
27 memset(tlb_store_tag
, -1, sizeof(tlb_store_tag
));
32 void* mmu_t::refill_tlb(reg_t addr
, reg_t bytes
, bool store
, bool fetch
)
34 reg_t idx
= (addr
>> PGSHIFT
) % TLB_ENTRIES
;
35 reg_t expected_tag
= addr
>> PGSHIFT
;
38 if (unlikely(!proc
)) {
39 pgbase
= addr
& -PGSIZE
;
41 reg_t mode
= get_field(proc
->state
.mstatus
, MSTATUS_PRV
);
42 if (!fetch
&& get_field(proc
->state
.mstatus
, MSTATUS_MPRV
))
43 mode
= get_field(proc
->state
.mstatus
, MSTATUS_PRV1
);
44 if (get_field(proc
->state
.mstatus
, MSTATUS_VM
) == VM_MBARE
)
48 reg_t msb_mask
= (reg_t(2) << (proc
->xlen
-1))-1; // zero-extend from xlen
49 pgbase
= addr
& -PGSIZE
& msb_mask
;
51 pgbase
= walk(addr
, mode
> PRV_U
, store
, fetch
);
55 reg_t pgoff
= addr
& (PGSIZE
-1);
56 reg_t paddr
= pgbase
+ pgoff
;
58 if (pgbase
>= memsz
) {
59 if (fetch
) throw trap_instruction_access_fault(addr
);
60 else if (store
) throw trap_store_access_fault(addr
);
61 else throw trap_load_access_fault(addr
);
64 bool trace
= tracer
.interested_in_range(pgbase
, pgbase
+ PGSIZE
, store
, fetch
);
65 if (unlikely(!fetch
&& trace
))
66 tracer
.trace(paddr
, bytes
, store
, fetch
);
69 if (tlb_load_tag
[idx
] != expected_tag
) tlb_load_tag
[idx
] = -1;
70 if (tlb_store_tag
[idx
] != expected_tag
) tlb_store_tag
[idx
] = -1;
71 if (tlb_insn_tag
[idx
] != expected_tag
) tlb_insn_tag
[idx
] = -1;
73 if (fetch
) tlb_insn_tag
[idx
] = expected_tag
;
74 else if (store
) tlb_store_tag
[idx
] = expected_tag
;
75 else tlb_load_tag
[idx
] = expected_tag
;
77 tlb_data
[idx
] = mem
+ pgbase
- (addr
& -PGSIZE
);
83 reg_t
mmu_t::walk(reg_t addr
, bool supervisor
, bool store
, bool fetch
)
85 int levels
, ptidxbits
, ptesize
;
86 switch (get_field(proc
->get_state()->mstatus
, MSTATUS_VM
))
88 case VM_SV32
: levels
= 2; ptidxbits
= 10; ptesize
= 4; break;
89 case VM_SV39
: levels
= 3; ptidxbits
= 9; ptesize
= 8; break;
90 case VM_SV48
: levels
= 4; ptidxbits
= 9; ptesize
= 8; break;
94 // verify bits xlen-1:va_bits-1 are all equal
95 int va_bits
= PGSHIFT
+ levels
* ptidxbits
;
96 reg_t mask
= (reg_t(1) << (proc
->xlen
- (va_bits
-1))) - 1;
97 reg_t masked_msbs
= (addr
>> (va_bits
-1)) & mask
;
98 if (masked_msbs
!= 0 && masked_msbs
!= mask
)
101 reg_t base
= proc
->get_state()->sptbr
;
102 int ptshift
= (levels
- 1) * ptidxbits
;
103 for (int i
= 0; i
< levels
; i
++, ptshift
-= ptidxbits
) {
104 reg_t idx
= (addr
>> (PGSHIFT
+ ptshift
)) & ((1 << ptidxbits
) - 1);
106 // check that physical address of PTE is legal
107 reg_t pte_addr
= base
+ idx
* ptesize
;
108 if (pte_addr
>= memsz
)
111 void* ppte
= mem
+ pte_addr
;
112 reg_t pte
= ptesize
== 4 ? *(uint32_t*)ppte
: *(uint64_t*)ppte
;
113 reg_t ppn
= pte
>> PTE_PPN_SHIFT
;
115 if (PTE_TABLE(pte
)) { // next level of page table
116 base
= ppn
<< PGSHIFT
;
117 } else if (!PTE_CHECK_PERM(pte
, supervisor
, store
, fetch
)) {
120 // set referenced and possibly dirty bits.
121 *(uint32_t*)ppte
|= PTE_R
| (store
* PTE_D
);
122 // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
123 reg_t vpn
= addr
>> PGSHIFT
;
124 reg_t addr
= (ppn
| (vpn
& ((reg_t(1) << ptshift
) - 1))) << PGSHIFT
;
126 // check that physical address is legal
137 void mmu_t::register_memtracer(memtracer_t
* t
)