1 // See LICENSE for license details.
11 #include "processor.h"
12 #include "memtracer.h"
16 // virtual memory configuration
18 const reg_t PGSIZE
= 1 << PGSHIFT
;
19 const reg_t PGMASK
= ~(PGSIZE
-1);
27 struct icache_entry_t
{
33 // this class implements a processor's port into the virtual memory system.
34 // an MMU and instruction cache are maintained for simulator performance.
38 mmu_t(sim_t
* sim
, processor_t
* proc
);
41 // template for functions that load an aligned value from memory
42 #define load_func(type) \
43 type##_t load_##type(reg_t addr) __attribute__((always_inline)) { \
44 if (addr & (sizeof(type##_t)-1)) \
45 throw trap_load_address_misaligned(addr); \
46 reg_t vpn = addr >> PGSHIFT; \
47 if (likely(tlb_load_tag[vpn % TLB_ENTRIES] == vpn)) \
48 return *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr); \
50 load_slow_path(addr, sizeof(type##_t), (uint8_t*)&res); \
54 // load value from memory at aligned address; zero extend to register width
60 // load value from memory at aligned address; sign extend to register width
66 // template for functions that store an aligned value to memory
67 #define store_func(type) \
68 void store_##type(reg_t addr, type##_t val) { \
69 if (addr & (sizeof(type##_t)-1)) \
70 throw trap_store_address_misaligned(addr); \
71 reg_t vpn = addr >> PGSHIFT; \
72 if (likely(tlb_store_tag[vpn % TLB_ENTRIES] == vpn)) \
73 *(type##_t*)(tlb_data[vpn % TLB_ENTRIES] + addr) = val; \
75 store_slow_path(addr, sizeof(type##_t), (const uint8_t*)&val); \
78 // store value to memory at aligned address
84 static const reg_t ICACHE_ENTRIES
= 1024;
86 inline size_t icache_index(reg_t addr
)
88 return (addr
/ PC_ALIGN
) % ICACHE_ENTRIES
;
91 inline icache_entry_t
* refill_icache(reg_t addr
, icache_entry_t
* entry
)
93 const uint16_t* iaddr
= translate_insn_addr(addr
);
94 insn_bits_t insn
= *iaddr
;
95 int length
= insn_length(insn
);
97 if (likely(length
== 4)) {
98 insn
|= (insn_bits_t
)*(const int16_t*)translate_insn_addr(addr
+ 2) << 16;
99 } else if (length
== 2) {
100 insn
= (int16_t)insn
;
101 } else if (length
== 6) {
102 insn
|= (insn_bits_t
)*(const int16_t*)translate_insn_addr(addr
+ 4) << 32;
103 insn
|= (insn_bits_t
)*(const uint16_t*)translate_insn_addr(addr
+ 2) << 16;
105 static_assert(sizeof(insn_bits_t
) == 8, "insn_bits_t must be uint64_t");
106 insn
|= (insn_bits_t
)*(const int16_t*)translate_insn_addr(addr
+ 6) << 48;
107 insn
|= (insn_bits_t
)*(const uint16_t*)translate_insn_addr(addr
+ 4) << 32;
108 insn
|= (insn_bits_t
)*(const uint16_t*)translate_insn_addr(addr
+ 2) << 16;
111 insn_fetch_t fetch
= {proc
->decode_insn(insn
), insn
};
115 reg_t paddr
= sim
->mem_to_addr((char*)iaddr
);
116 if (tracer
.interested_in_range(paddr
, paddr
+ 1, FETCH
)) {
118 tracer
.trace(paddr
, length
, FETCH
);
123 inline icache_entry_t
* access_icache(reg_t addr
)
125 icache_entry_t
* entry
= &icache
[icache_index(addr
)];
126 if (likely(entry
->tag
== addr
))
128 return refill_icache(addr
, entry
);
131 inline insn_fetch_t
load_insn(reg_t addr
)
133 return access_icache(addr
)->data
;
139 void register_memtracer(memtracer_t
*);
144 memtracer_list_t tracer
;
147 // implement an instruction cache for simulator performance
148 icache_entry_t icache
[ICACHE_ENTRIES
];
150 // implement a TLB for simulator performance
151 static const reg_t TLB_ENTRIES
= 256;
152 char* tlb_data
[TLB_ENTRIES
];
153 reg_t tlb_insn_tag
[TLB_ENTRIES
];
154 reg_t tlb_load_tag
[TLB_ENTRIES
];
155 reg_t tlb_store_tag
[TLB_ENTRIES
];
157 // finish translation on a TLB miss and update the TLB
158 void refill_tlb(reg_t vaddr
, reg_t paddr
, access_type type
);
159 const char* fill_from_mmio(reg_t vaddr
, reg_t paddr
);
161 // perform a page table walk for a given VA; set referenced/dirty bits
162 reg_t
walk(reg_t addr
, access_type type
, bool supervisor
, bool pum
);
164 // handle uncommon cases: TLB misses, page faults, MMIO
165 const uint16_t* fetch_slow_path(reg_t addr
);
166 void load_slow_path(reg_t addr
, reg_t len
, uint8_t* bytes
);
167 void store_slow_path(reg_t addr
, reg_t len
, const uint8_t* bytes
);
168 reg_t
translate(reg_t addr
, access_type type
);
171 const uint16_t* translate_insn_addr(reg_t addr
) __attribute__((always_inline
)) {
172 reg_t vpn
= addr
>> PGSHIFT
;
173 if (likely(tlb_insn_tag
[vpn
% TLB_ENTRIES
] == vpn
))
174 return (uint16_t*)(tlb_data
[vpn
% TLB_ENTRIES
] + addr
);
175 return fetch_slow_path(addr
);
178 friend class processor_t
;