10 #include "softfloat.h"
11 #include "platform.h" // softfloat isNaNF32UI, etc.
12 #include "internals.h" // ditto
14 processor_t::processor_t(sim_t
* _sim
, char* _mem
, size_t _memsz
)
15 : sim(_sim
), mmu(_mem
,_memsz
)
17 memset(XPR
,0,sizeof(XPR
));
18 memset(FPR
,0,sizeof(FPR
));
30 set_sr(SR_S
| SR_SX
); // SX ignored if 64b mode not supported
33 memset(counters
,0,sizeof(counters
));
43 for (int i
=0; i
<MAX_UTS
; i
++)
46 // a few assumptions about endianness, including freg_t union
47 static_assert(BYTE_ORDER
== LITTLE_ENDIAN
);
48 static_assert(sizeof(freg_t
) == 8);
49 static_assert(sizeof(reg_t
) == 8);
51 static_assert(sizeof(insn_t
) == 4);
52 static_assert(sizeof(uint128_t
) == 16 && sizeof(int128_t
) == 16);
55 void processor_t::init(uint32_t _id
, char* _mem
, size_t _memsz
)
59 for (int i
=0; i
<MAX_UTS
; i
++)
61 uts
[i
] = new processor_t(sim
, _mem
, _memsz
);
62 uts
[i
]->set_sr(uts
[i
]->sr
| SR_EF
);
63 uts
[i
]->set_sr(uts
[i
]->sr
| SR_EV
);
68 void processor_t::set_sr(uint32_t val
)
71 #ifndef RISCV_ENABLE_64BIT
72 sr
&= ~(SR_SX
| SR_UX
);
74 #ifndef RISCV_ENABLE_FPU
77 #ifndef RISCV_ENABLE_RVC
80 #ifndef RISCV_ENABLE_VEC
84 xprlen
= ((sr
& SR_S
) ? (sr
& SR_SX
) : (sr
& SR_UX
)) ? 64 : 32;
87 void processor_t::set_fsr(uint32_t val
)
89 fsr
= val
& ~FSR_ZERO
;
92 void processor_t::vcfg()
94 if (nxpr_use
== 0 && nfpr_use
== 0)
96 else if (nfpr_use
== 0)
97 vlmax
= (nxpr_all
-1) / (nxpr_use
-1);
98 else if (nxpr_use
== 0)
99 vlmax
= (nfpr_all
-1) / (nfpr_use
-1);
101 vlmax
= std::min((nxpr_all
-1) / (nxpr_use
-1), (nfpr_all
-1) / (nfpr_use
-1));
103 vlmax
= std::min(vlmax
, MAX_UTS
);
106 void processor_t::setvl(int vlapp
)
108 vl
= std::min(vlmax
, vlapp
);
111 void processor_t::step(size_t n
, bool noisy
)
118 uint32_t interrupts
= (cause
& CAUSE_IP
) >> CAUSE_IP_SHIFT
;
119 interrupts
&= (sr
& SR_IM
) >> SR_IM_SHIFT
;
120 if(interrupts
&& (sr
& SR_ET
))
121 take_trap(trap_interrupt
,noisy
);
123 insn_t insn
= mmu
.load_insn(pc
, sr
& SR_EC
);
125 reg_t npc
= pc
+ insn_length(insn
);
135 if(count
++ == compare
)
136 cause
|= 1 << (TIMER_IRQ
+CAUSE_IP_SHIFT
);
145 catch(vt_command_t cmd
)
147 if (cmd
== vt_command_stop
)
152 void processor_t::take_trap(trap_t t
, bool noisy
)
154 demand(t
< NUM_TRAPS
, "internal error: bad trap number %d", int(t
));
155 demand(sr
& SR_ET
, "error mode on core %d!\ntrap %s, pc 0x%016llx",
156 id
, trap_name(t
), (unsigned long long)pc
);
158 printf("core %3d: trap %s, pc 0x%016llx\n",
159 id
, trap_name(t
), (unsigned long long)pc
);
161 set_sr((((sr
& ~SR_ET
) | SR_S
) & ~SR_PS
) | ((sr
& SR_S
) ? SR_PS
: 0));
162 cause
= (cause
& ~CAUSE_EXCCODE
) | (t
<< CAUSE_EXCCODE_SHIFT
);
165 badvaddr
= mmu
.get_badvaddr();
168 void processor_t::disasm(insn_t insn
, reg_t pc
)
170 printf("core %3d: 0x%016llx (0x%08x) ",id
,(unsigned long long)pc
,insn
.bits
);
172 #ifdef RISCV_HAVE_LIBOPCODES
173 disassemble_info info
;
174 INIT_DISASSEMBLE_INFO(info
, stdout
, fprintf
);
175 info
.flavour
= bfd_target_unknown_flavour
;
176 info
.arch
= bfd_arch_mips
;
177 info
.mach
= 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
178 info
.endian
= BFD_ENDIAN_LITTLE
;
179 info
.buffer
= (bfd_byte
*)&insn
;
180 info
.buffer_length
= sizeof(insn
);
181 info
.buffer_vma
= pc
;
183 int ret
= print_insn_little_mips(pc
, &info
);
184 demand(ret
== (INSN_IS_RVC(insn
.bits
) ? 2 : 4), "disasm bug!");