57823f536a0f4c9d808635c20fa54ba627314fbd
1 // See LICENSE for license details.
10 #include "gdbserver.h"
23 processor_t::processor_t(const char* isa
, sim_t
* sim
, uint32_t id
,
25 : debug(false), sim(sim
), ext(NULL
), id(id
), halt_on_reset(halt_on_reset
)
27 parse_isa_string(isa
);
28 register_base_instructions();
30 mmu
= new mmu_t(sim
, this);
31 disassembler
= new disassembler_t(max_xlen
);
36 processor_t::~processor_t()
38 #ifdef RISCV_ENABLE_HISTOGRAM
39 if (histogram_enabled
)
41 fprintf(stderr
, "PC Histogram size:%zu\n", pc_histogram
.size());
42 for (auto it
: pc_histogram
)
43 fprintf(stderr
, "%0" PRIx64
" %" PRIu64
"\n", it
.first
, it
.second
);
51 static void bad_isa_string(const char* isa
)
53 fprintf(stderr
, "error: bad --isa option %s\n", isa
);
57 void processor_t::parse_isa_string(const char* str
)
59 std::string lowercase
, tmp
;
60 for (const char *r
= str
; *r
; r
++)
61 lowercase
+= std::tolower(*r
);
63 const char* p
= lowercase
.c_str();
64 const char* all_subsets
= "imafdc";
69 if (strncmp(p
, "rv32", 4) == 0)
70 max_xlen
= 32, isa
= reg_t(1) << 30, p
+= 4;
71 else if (strncmp(p
, "rv64", 4) == 0)
73 else if (strncmp(p
, "rv", 2) == 0)
78 } else if (*p
== 'g') { // treat "G" as "IMAFD"
79 tmp
= std::string("imafd") + (p
+1);
81 } else if (*p
!= 'i') {
85 isa_string
= "rv" + std::to_string(max_xlen
) + p
;
86 isa
|= 1L << ('s' - 'a'); // advertise support for supervisor mode
87 isa
|= 1L << ('u' - 'a'); // advertise support for user mode
90 isa
|= 1L << (*p
- 'a');
92 if (auto next
= strchr(all_subsets
, *p
)) {
93 all_subsets
= next
+ 1;
95 } else if (*p
== 'x') {
96 const char* ext
= p
+1, *end
= ext
;
99 register_extension(find_extension(std::string(ext
, end
- ext
).c_str())());
106 if (supports_extension('D') && !supports_extension('F'))
109 // advertise support for supervisor and user modes
110 isa
|= 1L << ('s' - 'a');
111 isa
|= 1L << ('u' - 'a');
114 void state_t::reset()
116 memset(this, 0, sizeof(*this));
119 mtvec
= DEFAULT_MTVEC
;
120 load_reservation
= -1;
122 for (unsigned int i
= 0; i
< num_triggers
; i
++)
123 mcontrol
[i
].type
= 2;
126 void processor_t::set_debug(bool value
)
130 ext
->set_debug(value
);
133 void processor_t::set_histogram(bool value
)
135 histogram_enabled
= value
;
136 #ifndef RISCV_ENABLE_HISTOGRAM
138 fprintf(stderr
, "PC Histogram support has not been properly enabled;");
139 fprintf(stderr
, " please re-build the riscv-isa-run project using \"configure --enable-histogram\".\n");
144 void processor_t::reset()
147 state
.dcsr
.halt
= halt_on_reset
;
148 halt_on_reset
= false;
149 set_csr(CSR_MSTATUS
, state
.mstatus
);
152 ext
->reset(); // reset the extension
155 void processor_t::raise_interrupt(reg_t which
)
157 throw trap_t(((reg_t
)1 << (max_xlen
-1)) | which
);
160 // Count number of contiguous 0 bits starting from the LSB.
161 static int ctz(reg_t val
)
165 while ((val
& 1) == 0)
170 void processor_t::take_interrupt()
172 reg_t pending_interrupts
= state
.mip
& state
.mie
;
174 reg_t mie
= get_field(state
.mstatus
, MSTATUS_MIE
);
175 reg_t m_enabled
= state
.prv
< PRV_M
|| (state
.prv
== PRV_M
&& mie
);
176 reg_t enabled_interrupts
= pending_interrupts
& ~state
.mideleg
& -m_enabled
;
178 reg_t sie
= get_field(state
.mstatus
, MSTATUS_SIE
);
179 reg_t s_enabled
= state
.prv
< PRV_S
|| (state
.prv
== PRV_S
&& sie
);
180 enabled_interrupts
|= pending_interrupts
& state
.mideleg
& -s_enabled
;
182 if (enabled_interrupts
)
183 raise_interrupt(ctz(enabled_interrupts
));
186 void processor_t::set_privilege(reg_t prv
)
188 assert(prv
<= PRV_M
);
195 void processor_t::enter_debug_mode(uint8_t cause
)
197 state
.dcsr
.cause
= cause
;
198 state
.dcsr
.prv
= state
.prv
;
199 set_privilege(PRV_M
);
200 state
.dpc
= state
.pc
;
201 state
.pc
= DEBUG_ROM_START
;
204 void processor_t::take_trap(trap_t
& t
, reg_t epc
)
207 fprintf(stderr
, "core %3d: exception %s, epc 0x%016" PRIx64
"\n",
210 fprintf(stderr
, "core %3d: badaddr 0x%016" PRIx64
"\n", id
,
214 if (t
.cause() == CAUSE_BREAKPOINT
&& (
215 (state
.prv
== PRV_M
&& state
.dcsr
.ebreakm
) ||
216 (state
.prv
== PRV_H
&& state
.dcsr
.ebreakh
) ||
217 (state
.prv
== PRV_S
&& state
.dcsr
.ebreaks
) ||
218 (state
.prv
== PRV_U
&& state
.dcsr
.ebreaku
))) {
219 enter_debug_mode(DCSR_CAUSE_SWBP
);
223 if (state
.dcsr
.cause
) {
224 state
.pc
= DEBUG_ROM_EXCEPTION
;
228 // by default, trap to M-mode, unless delegated to S-mode
229 reg_t bit
= t
.cause();
230 reg_t deleg
= state
.medeleg
;
231 if (bit
& ((reg_t
)1 << (max_xlen
-1)))
232 deleg
= state
.mideleg
, bit
&= ~((reg_t
)1 << (max_xlen
-1));
233 if (state
.prv
<= PRV_S
&& bit
< max_xlen
&& ((deleg
>> bit
) & 1)) {
234 // handle the trap in S-mode
235 state
.pc
= state
.stvec
;
236 state
.scause
= t
.cause();
239 state
.sbadaddr
= t
.get_badaddr();
241 reg_t s
= state
.mstatus
;
242 s
= set_field(s
, MSTATUS_SPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
243 s
= set_field(s
, MSTATUS_SPP
, state
.prv
);
244 s
= set_field(s
, MSTATUS_SIE
, 0);
245 set_csr(CSR_MSTATUS
, s
);
246 set_privilege(PRV_S
);
248 state
.pc
= state
.mtvec
;
250 state
.mcause
= t
.cause();
252 state
.mbadaddr
= t
.get_badaddr();
254 reg_t s
= state
.mstatus
;
255 s
= set_field(s
, MSTATUS_MPIE
, get_field(s
, MSTATUS_UIE
<< state
.prv
));
256 s
= set_field(s
, MSTATUS_MPP
, state
.prv
);
257 s
= set_field(s
, MSTATUS_MIE
, 0);
258 set_csr(CSR_MSTATUS
, s
);
259 set_privilege(PRV_M
);
262 yield_load_reservation();
265 void processor_t::disasm(insn_t insn
)
267 uint64_t bits
= insn
.bits() & ((1ULL << (8 * insn_length(insn
.bits()))) - 1);
268 fprintf(stderr
, "core %3d: 0x%016" PRIx64
" (0x%08" PRIx64
") %s\n",
269 id
, state
.pc
, bits
, disassembler
->disassemble(insn
).c_str());
272 static bool validate_vm(int max_xlen
, reg_t vm
)
274 if (max_xlen
== 64 && (vm
== VM_SV39
|| vm
== VM_SV48
))
276 if (max_xlen
== 32 && vm
== VM_SV32
)
278 return vm
== VM_MBARE
;
281 int processor_t::paddr_bits()
283 assert(xlen
== max_xlen
);
284 return max_xlen
== 64 ? 50 : 34;
287 void processor_t::set_csr(int which
, reg_t val
)
289 val
= zext_xlen(val
);
290 reg_t delegable_ints
= MIP_SSIP
| MIP_STIP
| MIP_SEIP
| (1 << IRQ_COP
);
291 reg_t all_ints
= delegable_ints
| MIP_MSIP
| MIP_MTIP
;
296 state
.fflags
= val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
);
300 state
.frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
304 state
.fflags
= (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
;
305 state
.frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
308 if ((val
^ state
.mstatus
) &
309 (MSTATUS_VM
| MSTATUS_MPP
| MSTATUS_MPRV
| MSTATUS_PUM
| MSTATUS_MXR
))
312 reg_t mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
313 | MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_PUM
314 | MSTATUS_MPP
| MSTATUS_MXR
| (ext
? MSTATUS_XS
: 0);
316 if (validate_vm(max_xlen
, get_field(val
, MSTATUS_VM
)))
319 state
.mstatus
= (state
.mstatus
& ~mask
) | (val
& mask
);
321 bool dirty
= (state
.mstatus
& MSTATUS_FS
) == MSTATUS_FS
;
322 dirty
|= (state
.mstatus
& MSTATUS_XS
) == MSTATUS_XS
;
324 state
.mstatus
= set_field(state
.mstatus
, MSTATUS32_SD
, dirty
);
326 state
.mstatus
= set_field(state
.mstatus
, MSTATUS64_SD
, dirty
);
328 // spike supports the notion of xlen < max_xlen, but current priv spec
329 // doesn't provide a mechanism to run RV32 software on an RV64 machine
334 reg_t mask
= MIP_SSIP
| MIP_STIP
;
335 state
.mip
= (state
.mip
& ~mask
) | (val
& mask
);
339 state
.mie
= (state
.mie
& ~all_ints
) | (val
& all_ints
);
342 state
.mideleg
= (state
.mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
346 #define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
347 #include "encoding.h"
349 state
.medeleg
= (state
.medeleg
& ~mask
) | (val
& mask
);
352 case CSR_MUCOUNTEREN
:
353 state
.mucounteren
= val
& 7;
355 case CSR_MSCOUNTEREN
:
356 state
.mscounteren
= val
& 7;
359 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
360 | SSTATUS_XS
| SSTATUS_PUM
;
361 return set_csr(CSR_MSTATUS
, (state
.mstatus
& ~mask
) | (val
& mask
));
364 return set_csr(CSR_MIP
,
365 (state
.mip
& ~state
.mideleg
) | (val
& state
.mideleg
));
367 return set_csr(CSR_MIE
,
368 (state
.mie
& ~state
.mideleg
) | (val
& state
.mideleg
));
370 // upper bits of sptbr are the ASID; we only support ASID = 0
371 state
.sptbr
= val
& (((reg_t
)1 << (paddr_bits() - PGSHIFT
)) - 1);
374 case CSR_SEPC
: state
.sepc
= val
; break;
375 case CSR_STVEC
: state
.stvec
= val
>> 2 << 2; break;
376 case CSR_SSCRATCH
: state
.sscratch
= val
; break;
377 case CSR_SCAUSE
: state
.scause
= val
; break;
378 case CSR_SBADADDR
: state
.sbadaddr
= val
; break;
379 case CSR_MEPC
: state
.mepc
= val
; break;
380 case CSR_MTVEC
: state
.mtvec
= val
>> 2 << 2; break;
381 case CSR_MSCRATCH
: state
.mscratch
= val
; break;
382 case CSR_MCAUSE
: state
.mcause
= val
; break;
383 case CSR_MBADADDR
: state
.mbadaddr
= val
; break;
385 if (val
< state
.num_triggers
) {
391 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
392 if (mc
->dmode
&& !state
.dcsr
.cause
) {
393 throw trap_illegal_instruction();
395 mc
->dmode
= get_field(val
, MCONTROL_DMODE(xlen
));
396 mc
->select
= get_field(val
, MCONTROL_SELECT
);
397 mc
->timing
= get_field(val
, MCONTROL_TIMING
);
398 mc
->action
= (mcontrol_action_t
) get_field(val
, MCONTROL_ACTION
);
399 mc
->chain
= get_field(val
, MCONTROL_CHAIN
);
400 mc
->match
= (mcontrol_match_t
) get_field(val
, MCONTROL_MATCH
);
401 mc
->m
= get_field(val
, MCONTROL_M
);
402 mc
->h
= get_field(val
, MCONTROL_H
);
403 mc
->s
= get_field(val
, MCONTROL_S
);
404 mc
->u
= get_field(val
, MCONTROL_U
);
405 mc
->execute
= get_field(val
, MCONTROL_EXECUTE
);
406 mc
->store
= get_field(val
, MCONTROL_STORE
);
407 mc
->load
= get_field(val
, MCONTROL_LOAD
);
408 // Assume we're here because of csrw.
413 if (state
.tselect
< state
.num_triggers
) {
414 state
.tdata2
[state
.tselect
] = val
;
418 state
.dcsr
.prv
= get_field(val
, DCSR_PRV
);
419 state
.dcsr
.step
= get_field(val
, DCSR_STEP
);
420 // TODO: ndreset and fullreset
421 state
.dcsr
.ebreakm
= get_field(val
, DCSR_EBREAKM
);
422 state
.dcsr
.ebreakh
= get_field(val
, DCSR_EBREAKH
);
423 state
.dcsr
.ebreaks
= get_field(val
, DCSR_EBREAKS
);
424 state
.dcsr
.ebreaku
= get_field(val
, DCSR_EBREAKU
);
425 state
.dcsr
.halt
= get_field(val
, DCSR_HALT
);
431 state
.dscratch
= val
;
436 reg_t
processor_t::get_csr(int which
)
442 if (!supports_extension('F'))
447 if (!supports_extension('F'))
452 if (!supports_extension('F'))
454 return (state
.fflags
<< FSR_AEXC_SHIFT
) | (state
.frm
<< FSR_RD_SHIFT
);
458 if ((state
.mucounteren
>> (which
& (xlen
-1))) & 1)
459 return get_csr(which
+ (CSR_MCYCLE
- CSR_CYCLE
));
464 if ((state
.mscounteren
>> (which
& (xlen
-1))) & 1)
465 return get_csr(which
+ (CSR_MCYCLE
- CSR_SCYCLE
));
467 case CSR_MUCOUNTEREN
: return state
.mucounteren
;
468 case CSR_MSCOUNTEREN
: return state
.mscounteren
;
469 case CSR_MUCYCLE_DELTA
: return 0;
470 case CSR_MUTIME_DELTA
: return 0;
471 case CSR_MUINSTRET_DELTA
: return 0;
472 case CSR_MSCYCLE_DELTA
: return 0;
473 case CSR_MSTIME_DELTA
: return 0;
474 case CSR_MSINSTRET_DELTA
: return 0;
475 case CSR_MUCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
476 case CSR_MUTIME_DELTAH
: if (xlen
> 32) break; else return 0;
477 case CSR_MUINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
478 case CSR_MSCYCLE_DELTAH
: if (xlen
> 32) break; else return 0;
479 case CSR_MSTIME_DELTAH
: if (xlen
> 32) break; else return 0;
480 case CSR_MSINSTRET_DELTAH
: if (xlen
> 32) break; else return 0;
481 case CSR_MCYCLE
: return state
.minstret
;
482 case CSR_MINSTRET
: return state
.minstret
;
483 case CSR_MCYCLEH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
484 case CSR_MINSTRETH
: if (xlen
> 32) break; else return state
.minstret
>> 32;
486 reg_t mask
= SSTATUS_SIE
| SSTATUS_SPIE
| SSTATUS_SPP
| SSTATUS_FS
487 | SSTATUS_XS
| SSTATUS_PUM
;
488 reg_t sstatus
= state
.mstatus
& mask
;
489 if ((sstatus
& SSTATUS_FS
) == SSTATUS_FS
||
490 (sstatus
& SSTATUS_XS
) == SSTATUS_XS
)
491 sstatus
|= (xlen
== 32 ? SSTATUS32_SD
: SSTATUS64_SD
);
494 case CSR_SIP
: return state
.mip
& state
.mideleg
;
495 case CSR_SIE
: return state
.mie
& state
.mideleg
;
496 case CSR_SEPC
: return state
.sepc
;
497 case CSR_SBADADDR
: return state
.sbadaddr
;
498 case CSR_STVEC
: return state
.stvec
;
501 return state
.scause
| ((state
.scause
>> (max_xlen
-1)) << (xlen
-1));
503 case CSR_SPTBR
: return state
.sptbr
;
504 case CSR_SSCRATCH
: return state
.sscratch
;
505 case CSR_MSTATUS
: return state
.mstatus
;
506 case CSR_MIP
: return state
.mip
;
507 case CSR_MIE
: return state
.mie
;
508 case CSR_MEPC
: return state
.mepc
;
509 case CSR_MSCRATCH
: return state
.mscratch
;
510 case CSR_MCAUSE
: return state
.mcause
;
511 case CSR_MBADADDR
: return state
.mbadaddr
;
512 case CSR_MISA
: return isa
;
513 case CSR_MARCHID
: return 0;
514 case CSR_MIMPID
: return 0;
515 case CSR_MVENDORID
: return 0;
516 case CSR_MHARTID
: return id
;
517 case CSR_MTVEC
: return state
.mtvec
;
518 case CSR_MEDELEG
: return state
.medeleg
;
519 case CSR_MIDELEG
: return state
.mideleg
;
520 case CSR_TSELECT
: return state
.tselect
;
522 if (state
.tselect
< state
.num_triggers
) {
524 mcontrol_t
*mc
= &state
.mcontrol
[state
.tselect
];
525 v
= set_field(v
, MCONTROL_TYPE(xlen
), mc
->type
);
526 v
= set_field(v
, MCONTROL_DMODE(xlen
), mc
->dmode
);
527 v
= set_field(v
, MCONTROL_MASKMAX(xlen
), mc
->maskmax
);
528 v
= set_field(v
, MCONTROL_SELECT
, mc
->select
);
529 v
= set_field(v
, MCONTROL_TIMING
, mc
->timing
);
530 v
= set_field(v
, MCONTROL_ACTION
, mc
->action
);
531 v
= set_field(v
, MCONTROL_CHAIN
, mc
->chain
);
532 v
= set_field(v
, MCONTROL_MATCH
, mc
->match
);
533 v
= set_field(v
, MCONTROL_M
, mc
->m
);
534 v
= set_field(v
, MCONTROL_H
, mc
->h
);
535 v
= set_field(v
, MCONTROL_S
, mc
->s
);
536 v
= set_field(v
, MCONTROL_U
, mc
->u
);
537 v
= set_field(v
, MCONTROL_EXECUTE
, mc
->execute
);
538 v
= set_field(v
, MCONTROL_STORE
, mc
->store
);
539 v
= set_field(v
, MCONTROL_LOAD
, mc
->load
);
546 if (state
.tselect
< state
.num_triggers
) {
547 return state
.tdata2
[state
.tselect
];
555 v
= set_field(v
, DCSR_XDEBUGVER
, 1);
556 v
= set_field(v
, DCSR_NDRESET
, 0);
557 v
= set_field(v
, DCSR_FULLRESET
, 0);
558 v
= set_field(v
, DCSR_PRV
, state
.dcsr
.prv
);
559 v
= set_field(v
, DCSR_STEP
, state
.dcsr
.step
);
560 v
= set_field(v
, DCSR_DEBUGINT
, sim
->debug_module
.get_interrupt(id
));
561 v
= set_field(v
, DCSR_STOPCYCLE
, 0);
562 v
= set_field(v
, DCSR_STOPTIME
, 0);
563 v
= set_field(v
, DCSR_EBREAKM
, state
.dcsr
.ebreakm
);
564 v
= set_field(v
, DCSR_EBREAKH
, state
.dcsr
.ebreakh
);
565 v
= set_field(v
, DCSR_EBREAKS
, state
.dcsr
.ebreaks
);
566 v
= set_field(v
, DCSR_EBREAKU
, state
.dcsr
.ebreaku
);
567 v
= set_field(v
, DCSR_HALT
, state
.dcsr
.halt
);
568 v
= set_field(v
, DCSR_CAUSE
, state
.dcsr
.cause
);
574 return state
.dscratch
;
576 throw trap_illegal_instruction();
579 reg_t
illegal_instruction(processor_t
* p
, insn_t insn
, reg_t pc
)
581 throw trap_illegal_instruction();
584 insn_func_t
processor_t::decode_insn(insn_t insn
)
586 // look up opcode in hash table
587 size_t idx
= insn
.bits() % OPCODE_CACHE_SIZE
;
588 insn_desc_t desc
= opcode_cache
[idx
];
590 if (unlikely(insn
.bits() != desc
.match
)) {
591 // fall back to linear search
592 insn_desc_t
* p
= &instructions
[0];
593 while ((insn
.bits() & p
->mask
) != p
->match
)
597 if (p
->mask
!= 0 && p
> &instructions
[0]) {
598 if (p
->match
!= (p
-1)->match
&& p
->match
!= (p
+1)->match
) {
599 // move to front of opcode list to reduce miss penalty
600 while (--p
>= &instructions
[0])
602 instructions
[0] = desc
;
606 opcode_cache
[idx
] = desc
;
607 opcode_cache
[idx
].match
= insn
.bits();
610 return xlen
== 64 ? desc
.rv64
: desc
.rv32
;
613 void processor_t::register_insn(insn_desc_t desc
)
615 instructions
.push_back(desc
);
618 void processor_t::build_opcode_map()
621 bool operator()(const insn_desc_t
& lhs
, const insn_desc_t
& rhs
) {
622 if (lhs
.match
== rhs
.match
)
623 return lhs
.mask
> rhs
.mask
;
624 return lhs
.match
> rhs
.match
;
627 std::sort(instructions
.begin(), instructions
.end(), cmp());
629 for (size_t i
= 0; i
< OPCODE_CACHE_SIZE
; i
++)
630 opcode_cache
[i
] = {0, 0, &illegal_instruction
, &illegal_instruction
};
633 void processor_t::register_extension(extension_t
* x
)
635 for (auto insn
: x
->get_instructions())
638 for (auto disasm_insn
: x
->get_disasms())
639 disassembler
->add_insn(disasm_insn
);
641 throw std::logic_error("only one extension may be registered");
643 x
->set_processor(this);
646 void processor_t::register_base_instructions()
648 #define DECLARE_INSN(name, match, mask) \
649 insn_bits_t name##_match = (match), name##_mask = (mask);
650 #include "encoding.h"
653 #define DEFINE_INSN(name) \
654 REGISTER_INSN(this, name, name##_match, name##_mask)
655 #include "insn_list.h"
658 register_insn({0, 0, &illegal_instruction
, &illegal_instruction
});
662 bool processor_t::load(reg_t addr
, size_t len
, uint8_t* bytes
)
667 bool processor_t::store(reg_t addr
, size_t len
, const uint8_t* bytes
)
672 state
.mip
&= ~MIP_MSIP
;
674 state
.mip
|= MIP_MSIP
;
682 void processor_t::trigger_updated()
685 mmu
->check_triggers_fetch
= false;
686 mmu
->check_triggers_load
= false;
687 mmu
->check_triggers_store
= false;
689 for (unsigned i
= 0; i
< state
.num_triggers
; i
++) {
690 if (state
.mcontrol
[i
].execute
) {
691 mmu
->check_triggers_fetch
= true;
693 if (state
.mcontrol
[i
].load
) {
694 mmu
->check_triggers_load
= true;
696 if (state
.mcontrol
[i
].store
) {
697 mmu
->check_triggers_store
= true;